src/soc/fu/alu/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import (TestCase, ALUHelpers)
  16 from soc.fu.alu.pipeline import ALUBasePipe
  17 from soc.fu.alu.pipe_data import ALUPipeSpec
  18 import random
  19
  20
  21 def get_cu_inputs(dec2, sim):
  22     """naming (res) must conform to ALUFunctionUnit input regspec
  23     """
  24     res = {}
  25
  26     # RA (or RC)
  27     reg1_ok = yield dec2.e.read_reg1.ok
  28     if reg1_ok:
  29         data1 = yield dec2.e.read_reg1.data
  30         res['ra'] = sim.gpr(data1).value
  31
  32     # RB (or immediate)
  33     reg2_ok = yield dec2.e.read_reg2.ok
  34     if reg2_ok:
  35         data2 = yield dec2.e.read_reg2.data
  36         res['rb'] = sim.gpr(data2).value
  37
  38     # XER.ca
  39     cry_in = yield dec2.e.input_carry
  40     if cry_in == CryIn.CA.value:
  41         carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  42         carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  43         res['xer_ca'] = carry | (carry32<<1)
  44
  45     # XER.so
  46     oe = yield dec2.e.oe.data[0] & dec2.e.oe.ok
  47     if oe:
  48         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
  49         res['xer_so'] = so
  50
  51     print ("alu get_cu_inputs", res)
  52
  53     return res
  54
  55
  56
  57 def set_alu_inputs(alu, dec2, sim):
  58     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  59     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  60     # and place it into data_i.b
  61
  62     inp = yield from get_cu_inputs(dec2, sim)
  63     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  64     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  65
  66     yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
  67     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  68
  69
  70 # This test bench is a bit different than is usual. Initially when I
  71 # was writing it, I had all of the tests call a function to create a
  72 # device under test and simulator, initialize the dut, run the
  73 # simulation for ~2 cycles, and assert that the dut output what it
  74 # should have. However, this was really slow, since it needed to
  75 # create and tear down the dut and simulator for every test case.
  76
  77 # Now, instead of doing that, every test case in ALUTestCase puts some
  78 # data into the test_data list below, describing the instructions to
  79 # be tested and the initial state. Once all the tests have been run,
  80 # test_data gets passed to TestRunner which then sets up the DUT and
  81 # simulator once, runs all the data through it, and asserts that the
  82 # results match the pseudocode sim at every cycle.
  83
  84 # By doing this, I've reduced the time it takes to run the test suite
  85 # massively. Before, it took around 1 minute on my computer, now it
  86 # takes around 3 seconds
  87
  88
  89 class ALUTestCase(FHDLTestCase):
  90     test_data = []
  91
  92     def __init__(self, name):
  93         super().__init__(name)
  94         self.test_name = name
  95
  96     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  97         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  98         self.test_data.append(tc)
  99
 100     def test_1_regression(self):
 101         lst = [f"extsw 3, 1"]
 102         initial_regs = [0] * 32
 103         initial_regs[1] = 0xb6a1fc6c8576af91
 104         self.run_tst_program(Program(lst), initial_regs)
 105         lst = [f"subf 3, 1, 2"]
 106         initial_regs = [0] * 32
 107         initial_regs[1] = 0x3d7f3f7ca24bac7b
 108         initial_regs[2] = 0xf6b2ac5e13ee15c2
 109         self.run_tst_program(Program(lst), initial_regs)
 110         lst = [f"subf 3, 1, 2"]
 111         initial_regs = [0] * 32
 112         initial_regs[1] = 0x833652d96c7c0058
 113         initial_regs[2] = 0x1c27ecff8a086c1a
 114         self.run_tst_program(Program(lst), initial_regs)
 115         lst = [f"extsb 3, 1"]
 116         initial_regs = [0] * 32
 117         initial_regs[1] = 0x7f9497aaff900ea0
 118         self.run_tst_program(Program(lst), initial_regs)
 119         lst = [f"add. 3, 1, 2"]
 120         initial_regs = [0] * 32
 121         initial_regs[1] = 0xc523e996a8ff6215
 122         initial_regs[2] = 0xe1e5b9cc9864c4a8
 123         self.run_tst_program(Program(lst), initial_regs)
 124         lst = [f"add 3, 1, 2"]
 125         initial_regs = [0] * 32
 126         initial_regs[1] = 0x2e08ae202742baf8
 127         initial_regs[2] = 0x86c43ece9efe5baa
 128         self.run_tst_program(Program(lst), initial_regs)
 129
 130     def test_rand(self):
 131         insns = ["add", "add.", "subf"]
 132         for i in range(40):
 133             choice = random.choice(insns)
 134             lst = [f"{choice} 3, 1, 2"]
 135             initial_regs = [0] * 32
 136             initial_regs[1] = random.randint(0, (1<<64)-1)
 137             initial_regs[2] = random.randint(0, (1<<64)-1)
 138             self.run_tst_program(Program(lst), initial_regs)
 139
 140     def test_rand_imm(self):
 141         insns = ["addi", "addis", "subfic"]
 142         for i in range(10):
 143             choice = random.choice(insns)
 144             imm = random.randint(-(1<<15), (1<<15)-1)
 145             lst = [f"{choice} 3, 1, {imm}"]
 146             print(lst)
 147             initial_regs = [0] * 32
 148             initial_regs[1] = random.randint(0, (1<<64)-1)
 149             self.run_tst_program(Program(lst), initial_regs)
 150
 151     def test_0_adde(self):
 152         lst = ["adde. 5, 6, 7"]
 153         for i in range(10):
 154             initial_regs = [0] * 32
 155             initial_regs[6] = random.randint(0, (1<<64)-1)
 156             initial_regs[7] = random.randint(0, (1<<64)-1)
 157             initial_sprs = {}
 158             xer = SelectableInt(0, 64)
 159             xer[XER_bits['CA']] = 1
 160             initial_sprs[special_sprs['XER']] = xer
 161             self.run_tst_program(Program(lst), initial_regs, initial_sprs)
 162
 163     def test_cmp(self):
 164         lst = ["subf. 1, 6, 7",
 165                "cmp cr2, 1, 6, 7"]
 166         initial_regs = [0] * 32
 167         initial_regs[6] = 0x10
 168         initial_regs[7] = 0x05
 169         self.run_tst_program(Program(lst), initial_regs, {})
 170
 171     def test_extsb(self):
 172         insns = ["extsb", "extsh", "extsw"]
 173         for i in range(10):
 174             choice = random.choice(insns)
 175             lst = [f"{choice} 3, 1"]
 176             print(lst)
 177             initial_regs = [0] * 32
 178             initial_regs[1] = random.randint(0, (1<<64)-1)
 179             self.run_tst_program(Program(lst), initial_regs)
 180
 181     def test_cmpeqb(self):
 182         lst = ["cmpeqb cr1, 1, 2"]
 183         for i in range(20):
 184             initial_regs = [0] * 32
 185             initial_regs[1] = i
 186             initial_regs[2] = 0x0001030507090b0f
 187             self.run_tst_program(Program(lst), initial_regs, {})
 188
 189     def test_ilang(self):
 190         pspec = ALUPipeSpec(id_wid=2)
 191         alu = ALUBasePipe(pspec)
 192         vl = rtlil.convert(alu, ports=alu.ports())
 193         with open("alu_pipeline.il", "w") as f:
 194             f.write(vl)
 195
 196
 197 class TestRunner(FHDLTestCase):
 198     def __init__(self, test_data):
 199         super().__init__("run_all")
 200         self.test_data = test_data
 201
 202     def run_all(self):
 203         m = Module()
 204         comb = m.d.comb
 205         instruction = Signal(32)
 206
 207         pdecode = create_pdecode()
 208
 209         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 210
 211         pspec = ALUPipeSpec(id_wid=2)
 212         m.submodules.alu = alu = ALUBasePipe(pspec)
 213
 214         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 215         comb += alu.p.valid_i.eq(1)
 216         comb += alu.n.ready_i.eq(1)
 217         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 218         sim = Simulator(m)
 219
 220         sim.add_clock(1e-6)
 221         def process():
 222             for test in self.test_data:
 223                 print(test.name)
 224                 program = test.program
 225                 self.subTest(test.name)
 226                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
 227                                 test.mem, test.msr)
 228                 gen = program.generate_instructions()
 229                 instructions = list(zip(gen, program.assembly.splitlines()))
 230
 231                 index = sim.pc.CIA.value//4
 232                 while index < len(instructions):
 233                     ins, code = instructions[index]
 234
 235                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 236                     print(code)
 237                     if 'XER' in sim.spr:
 238                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 239                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 240                         ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 241                         print ("before: so/ov/32", so, ov, ov32)
 242
 243                     # ask the decoder to decode this binary data (endian'd)
 244                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 245                     yield instruction.eq(ins)          # raw binary instr.
 246                     yield Settle()
 247                     fn_unit = yield pdecode2.e.fn_unit
 248                     self.assertEqual(fn_unit, Function.ALU.value)
 249                     yield from set_alu_inputs(alu, pdecode2, sim)
 250                     yield
 251                     opname = code.split(' ')[0]
 252                     yield from sim.call(opname)
 253                     index = sim.pc.CIA.value//4
 254
 255                     vld = yield alu.n.valid_o
 256                     while not vld:
 257                         yield
 258                         vld = yield alu.n.valid_o
 259                     yield
 260                     alu_out = yield alu.n.data_o.o.data
 261                     out_reg_valid = yield pdecode2.e.write_reg.ok
 262                     if out_reg_valid:
 263                         write_reg_idx = yield pdecode2.e.write_reg.data
 264                         expected = sim.gpr(write_reg_idx).value
 265                         print(f"expected {expected:x}, actual: {alu_out:x}")
 266                         self.assertEqual(expected, alu_out, code)
 267                     yield from self.check_extra_alu_outputs(alu, pdecode2,
 268                                                             sim, code)
 269
 270         sim.add_sync_process(process)
 271         with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
 272                             traces=[]):
 273             sim.run()
 274
 275     def check_extra_alu_outputs(self, alu, dec2, sim, code):
 276         rc = yield dec2.e.rc.data
 277         op = yield dec2.e.insn_type
 278         cridx_ok = yield dec2.e.write_cr.ok
 279         cridx = yield dec2.e.write_cr.data
 280
 281         print ("check extra output", repr(code), cridx_ok, cridx)
 282         if rc:
 283             self.assertEqual(cridx, 0, code)
 284
 285         if cridx_ok:
 286             cr_expected = sim.crl[cridx].get_range().value
 287             cr_actual = yield alu.n.data_o.cr0.data
 288             print ("CR", cridx, cr_expected, cr_actual)
 289             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
 290
 291         cry_out = yield dec2.e.output_carry
 292         if cry_out:
 293             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 294             real_carry = yield alu.n.data_o.xer_ca.data[0] # XXX CA not CA32
 295             self.assertEqual(expected_carry, real_carry, code)
 296             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 297             real_carry32 = yield alu.n.data_o.xer_ca.data[1] # XXX CA32
 298             self.assertEqual(expected_carry32, real_carry32, code)
 299
 300         oe = yield dec2.e.oe.oe
 301         oe_ok = yield dec2.e.oe.ok
 302         if oe and oe_ok:
 303             expected_so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 304             real_so = yield alu.n.data_o.xer_so.data[0]
 305             self.assertEqual(expected_so, real_so, code)
 306             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 307             real_ov = yield alu.n.data_o.xer_ov.data[0] # OV bit
 308             self.assertEqual(expected_ov, real_ov, code)
 309             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 310             real_ov32 = yield alu.n.data_o.xer_ov.data[1] # OV32 bit
 311             self.assertEqual(expected_ov32, real_ov32, code)
 312             print ("after: so/ov/32", real_so, real_ov, real_ov32)
 313         else:
 314             # if OE not enabled, XER SO and OV must correspondingly be false
 315             so_ok = yield alu.n.data_o.xer_so.ok
 316             ov_ok = yield alu.n.data_o.xer_ov.ok
 317             self.assertEqual(so_ok, False, code)
 318             self.assertEqual(ov_ok, False, code)
 319
 320
 321
 322 if __name__ == "__main__":
 323     unittest.main(exit=False)
 324     suite = unittest.TestSuite()
 325     suite.addTest(TestRunner(ALUTestCase.test_data))
 326
 327     runner = unittest.TextTestRunner()
 328     runner.run(suite)