2 Optional Register allocation listed below. mandatory input
3 (CompBROpSubset, CIA) not included.
5 * CR is Condition Register (not an SPR)
6 * SPR1 and SPR2 are all from the SPR regfile. 2 ports are needed
23 op_bctarl CR, TAR, CTR
26 from nmigen
import Signal
, Const
, Cat
27 from ieee754
.fpcommon
.getop
import FPPipeContext
28 from soc
.decoder
.power_decoder2
import Data
29 from soc
.fu
.pipe_data
import IntegerData
, CommonPipeSpec
30 from soc
.fu
.branch
.br_input_record
import CompBROpSubset
# TODO: replace
33 class BranchInputData(IntegerData
):
34 regspec
= [('FAST', 'spr1', '0:63'),
35 ('FAST', 'spr2', '0:63'),
36 ('CR', 'cr_a', '0:3'),
37 ('FAST', 'cia', '0:63')]
38 def __init__(self
, pspec
):
39 super().__init
__(pspec
)
40 # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
41 # this involves the *decode* unit selecting the register, based
42 # on detecting the operand being bcctr, bclr or bctar
44 self
.spr1
= Signal(64, reset_less
=True) # see table above, SPR1
45 self
.spr2
= Signal(64, reset_less
=True) # see table above, SPR2
46 self
.cr_a
= Signal(4, reset_less
=True) # Condition Register(s) CR0-7
47 self
.cia
= Signal(64, reset_less
=True) # Current Instruction Address
49 # convenience variables. not all of these are used at once
51 self
.lr
= self
.tar
= self
.spr2
55 yield from super().__iter
__()
63 return lst
+ [self
.spr1
.eq(i
.spr1
), self
.spr2
.eq(i
.spr2
),
64 self
.cr_a
.eq(i
.cr_a
), self
.cia
.eq(i
.cia
)]
67 class BranchOutputData(IntegerData
):
68 regspec
= [('FAST', 'spr1', '0:63'),
69 ('FAST', 'spr2', '0:63'),
70 ('FAST', 'nia', '0:63')]
71 def __init__(self
, pspec
):
72 super().__init
__(pspec
)
73 self
.spr1
= Data(64, name
="spr1")
74 self
.spr2
= Data(64, name
="spr2")
75 self
.nia
= Data(64, name
="nia")
77 # convenience variables.
79 self
.lr
= self
.tar
= self
.spr2
82 yield from super().__iter
__()
89 return lst
+ [self
.spr1
.eq(i
.spr1
), self
.spr2
.eq(i
.spr2
),
93 class BranchPipeSpec(CommonPipeSpec
):
94 regspec
= (BranchInputData
.regspec
, BranchOutputData
.regspec
)
95 opsubsetkls
= CompBROpSubset
96 def rdflags(self
, e
): # in order of regspec
97 cr1_en
= e
.read_cr1
.ok
# CR A
98 fast1_ok
= e
.read_fast1
.ok
# SPR1
99 fast2_ok
= e
.read_fast2
.ok
# SPR2
100 return Cat(fast1_ok
, fast2_ok
, cr1_en
, 1) # SPR1 SPR2 CR CIA