2 Optional Register allocation listed below. mandatory input
3 (CompBROpSubset, CIA) not included.
5 * CR is Condition Register (not an SPR)
6 * SPR1 and SPR2 are all from the SPR regfile. 2 ports are needed
23 op_bctarl CR, TAR, CTR
26 from soc
.fu
.pipe_data
import IntegerData
, CommonPipeSpec
27 from soc
.fu
.branch
.br_input_record
import CompBROpSubset
# TODO: replace
30 class BranchInputData(IntegerData
):
31 # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
32 # this involves the *decode* unit selecting the register, based
33 # on detecting the operand being bcctr, bclr or bctar
34 regspec
= [('FAST', 'spr1', '0:63'), # see table above, SPR1
35 ('FAST', 'spr2', '0:63'), # see table above, SPR2
36 ('CR', 'cr_a', '0:3'), # Condition Register(s) CR0-7
37 ('FAST', 'cia', '0:63')] # Current Instruction Address
38 def __init__(self
, pspec
):
39 super().__init
__(pspec
, False)
41 # convenience variables. not all of these are used at once
43 self
.lr
= self
.tar
= self
.spr2
47 class BranchOutputData(IntegerData
):
48 regspec
= [('FAST', 'spr1', '0:63'),
49 ('FAST', 'spr2', '0:63'),
50 ('FAST', 'nia', '0:63')]
51 def __init__(self
, pspec
):
52 super().__init
__(pspec
, True)
54 # convenience variables.
56 self
.lr
= self
.tar
= self
.spr2
59 class BranchPipeSpec(CommonPipeSpec
):
60 regspec
= (BranchInputData
.regspec
, BranchOutputData
.regspec
)
61 opsubsetkls
= CompBROpSubset