1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.decoder
.power_enums
import Function
9 from soc
.decoder
.isa
.all
import ISA
11 from soc
.experiment
.compalu_multi
import find_ok
# hack
14 def set_cu_input(cu
, idx
, data
):
15 rdop
= cu
.get_in_name(idx
)
16 yield cu
.src_i
[idx
].eq(data
)
18 rd_rel_o
= yield cu
.rd
.rel
[idx
]
19 print ("rd_rel %d wait HI" % idx
, rd_rel_o
, rdop
, hex(data
))
23 yield cu
.rd
.go
[idx
].eq(1)
26 rd_rel_o
= yield cu
.rd
.rel
[idx
]
29 print ("rd_rel %d wait HI" % idx
, rd_rel_o
)
31 yield cu
.rd
.go
[idx
].eq(0)
32 yield cu
.src_i
[idx
].eq(0)
35 def get_cu_output(cu
, idx
, code
):
36 wrmask
= yield cu
.wrmask
37 wrop
= cu
.get_out_name(idx
)
38 wrok
= cu
.get_out(idx
)
39 fname
= find_ok(wrok
.fields
)
40 wrok
= yield getattr(wrok
, fname
)
41 print ("wr_rel mask", repr(code
), idx
, wrop
, bin(wrmask
), fname
, wrok
)
42 assert wrmask
& (1<<idx
), \
43 "get_cu_output '%s': mask bit %d not set\n" \
44 "write-operand '%s' Data.ok likely not set (%s)" \
45 % (code
, idx
, wrop
, hex(wrok
))
47 wr_relall_o
= yield cu
.wr
.rel
48 wr_rel_o
= yield cu
.wr
.rel
[idx
]
49 print ("wr_rel %d wait" % idx
, hex(wr_relall_o
), wr_rel_o
)
53 yield cu
.wr
.go
[idx
].eq(1)
55 result
= yield cu
.dest
[idx
]
57 yield cu
.wr
.go
[idx
].eq(0)
58 print ("result", repr(code
), idx
, wrop
, wrok
, hex(result
))
62 def set_cu_inputs(cu
, inp
):
63 for idx
, data
in inp
.items():
64 yield from set_cu_input(cu
, idx
, data
)
67 def set_operand(cu
, dec2
, sim
):
68 yield from cu
.oper_i
.eq_from_execute1(dec2
.e
)
69 yield cu
.issue_i
.eq(1)
71 yield cu
.issue_i
.eq(0)
75 def get_cu_outputs(cu
, code
):
77 wrmask
= yield cu
.wrmask
78 print ("get_cu_outputs", cu
.n_dst
, wrmask
)
79 if not wrmask
: # no point waiting (however really should doublecheck wr.rel)
81 # wait for at least one result
83 wr_rel_o
= yield cu
.wr
.rel
87 for i
in range(cu
.n_dst
):
88 wr_rel_o
= yield cu
.wr
.rel
[i
]
90 result
= yield from get_cu_output(cu
, i
, code
)
91 wrop
= cu
.get_out_name(i
)
92 print ("output", i
, wrop
, hex(result
))
97 def get_inp_indexed(cu
, inp
):
99 for i
in range(cu
.n_src
):
100 wrop
= cu
.get_in_name(i
)
106 class TestRunner(FHDLTestCase
):
107 def __init__(self
, test_data
, fukls
, iodef
, funit
):
108 super().__init
__("run_all")
109 self
.test_data
= test_data
117 instruction
= Signal(32)
119 pdecode
= create_pdecode()
121 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
122 if self
.funit
== Function
.LDST
:
123 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
124 m
.submodules
.l0
= l0
= TstL0CacheBuffer(n_units
=1, regwid
=64)
125 pi
= l0
.l0
.dports
[0].pi
126 m
.submodules
.cu
= cu
= self
.fukls(pi
, awid
=4)
127 m
.d
.comb
+= cu
.ad
.go
.eq(cu
.ad
.rel
) # link addr-go direct to rel
129 m
.submodules
.cu
= cu
= self
.fukls()
131 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
137 yield cu
.issue_i
.eq(0)
140 for test
in self
.test_data
:
142 program
= test
.program
143 self
.subTest(test
.name
)
144 print ("test", test
.name
, test
.mem
)
145 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
)
146 gen
= program
.generate_instructions()
147 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
149 index
= sim
.pc
.CIA
.value
//4
150 while index
< len(instructions
):
151 ins
, code
= instructions
[index
]
153 print("0x{:X}".format(ins
& 0xffffffff))
156 # ask the decoder to decode this binary data (endian'd)
157 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
158 yield instruction
.eq(ins
) # raw binary instr.
160 fn_unit
= yield pdecode2
.e
.fn_unit
161 fuval
= self
.funit
.value
162 self
.assertEqual(fn_unit
& fuval
, fuval
)
164 # set operand and get inputs
165 yield from set_operand(cu
, pdecode2
, sim
)
166 iname
= yield from self
.iodef
.get_cu_inputs(pdecode2
, sim
)
167 inp
= get_inp_indexed(cu
, iname
)
169 # reset read-operand mask
170 rdmask
= pdecode2
.rdflags(cu
)
171 #print ("hardcoded rdmask", cu.rdflags(pdecode2.e))
172 #print ("decoder rdmask", rdmask)
173 yield cu
.rdmaskn
.eq(~rdmask
)
175 # reset write-operand mask
176 for idx
in range(cu
.n_dst
):
177 wrok
= cu
.get_out(idx
)
178 fname
= find_ok(wrok
.fields
)
179 yield getattr(wrok
, fname
).eq(0)
184 rd_rel_o
= yield cu
.rd
.rel
185 wr_rel_o
= yield cu
.wr
.rel
186 print ("before inputs, rd_rel, wr_rel: ",
187 bin(rd_rel_o
), bin(wr_rel_o
))
188 assert wr_rel_o
== 0, "wr.rel %s must be zero. "\
189 "previous instr not written all regs\n"\
191 (bin(wr_rel_o
), cu
.rwid
[1])
192 yield from set_cu_inputs(cu
, inp
)
194 rd_rel_o
= yield cu
.rd
.rel
195 wr_rel_o
= yield cu
.wr
.rel
196 wrmask
= yield cu
.wrmask
197 print ("after inputs, rd_rel, wr_rel, wrmask: ",
198 bin(rd_rel_o
), bin(wr_rel_o
), bin(wrmask
))
200 # call simulated operation
201 opname
= code
.split(' ')[0]
202 yield from sim
.call(opname
)
203 index
= sim
.pc
.CIA
.value
//4
206 # get all outputs (one by one, just "because")
207 res
= yield from get_cu_outputs(cu
, code
)
209 yield from self
.iodef
.check_cu_outputs(res
, pdecode2
,
212 # sigh. hard-coded. test memory
213 if self
.funit
== Function
.LDST
:
214 print ("mem dump", sim
.mem
.mem
)
216 sim
.add_sync_process(process
)
218 name
= self
.funit
.name
.lower()
219 with sim
.write_vcd("%s_simulator.vcd" % name
,
220 "%s_simulator.gtkw" % name
,