src/soc/fu/compunits/test/test_cr_compunit.py

   1 import unittest
   2 from openpower.decoder.power_enums import (XER_bits, Function)
   3
   4 # XXX bad practice: use of global variables
   5 from soc.fu.cr.test.test_pipe_caller import get_cu_inputs
   6 from soc.fu.cr.test.test_pipe_caller import CRTestCase
   7
   8 from soc.fu.compunits.compunits import CRFunctionUnit
   9 from soc.fu.compunits.test.test_compunit import TestRunner
  10 from openpower.util import mask_extend
  11 from openpower.endian import bigendian
  12
  13
  14 class CRTestRunner(TestRunner):
  15     def __init__(self, test_data):
  16         super().__init__(test_data, CRFunctionUnit, self,
  17                          Function.CR, bigendian)
  18
  19     def get_cu_inputs(self, dec2, sim):
  20         """naming (res) must conform to CRFunctionUnit input regspec
  21         """
  22         res = yield from get_cu_inputs(dec2, sim)
  23         return res
  24
  25     def check_cu_outputs(self, res, dec2, sim, alu, code):
  26         """naming (res) must conform to CRFunctionUnit output regspec
  27         """
  28
  29         print("check extra output", repr(code), res)
  30
  31         # full CR
  32         whole_reg_ok = yield dec2.e.do.write_cr_whole.ok
  33         whole_reg_data = yield dec2.e.do.write_cr_whole.data
  34         full_cr_mask = mask_extend(whole_reg_data, 8, 4)
  35
  36         cr_en = yield dec2.e.write_cr.ok
  37         if whole_reg_ok:
  38             full_cr = res['full_cr']
  39             expected_cr = sim.cr.value
  40             print("CR whole: expected %x, actual: %x mask: %x" % \
  41                 (expected_cr, full_cr, full_cr_mask))
  42             self.assertEqual(expected_cr & full_cr_mask,
  43                              full_cr & full_cr_mask, code)
  44
  45         # part-CR
  46         if cr_en:
  47             cr_sel = yield dec2.e.write_cr.data
  48             expected_cr = sim.crl[cr_sel].get_range().value
  49             real_cr = res['cr_a']
  50             self.assertEqual(expected_cr, real_cr, code)
  51
  52         # RT
  53         out_reg_valid = yield dec2.e.write_reg.ok
  54         if out_reg_valid:
  55             alu_out = res['o']
  56             write_reg_idx = yield dec2.e.write_reg.data
  57             expected = sim.gpr(write_reg_idx).value
  58             print(f"expected {expected:x}, actual: {alu_out:x}")
  59             self.assertEqual(expected, alu_out, code)
  60
  61
  62 if __name__ == "__main__":
  63     unittest.main(exit=False)
  64     suite = unittest.TestSuite()
  65     suite.addTest(CRTestRunner(CRTestCase().test_data))
  66
  67     runner = unittest.TextTestRunner()
  68     runner.run(suite)