2 from openpower
.decoder
.power_enums
import (XER_bits
, Function
)
4 from soc
.fu
.ldst
.test
.test_pipe_caller
import LDSTTestCase
, get_cu_inputs
6 from soc
.fu
.compunits
.compunits
import LDSTFunctionUnit
7 from soc
.fu
.compunits
.test
.test_compunit
import TestRunner
8 from soc
.fu
.test
.common
import ALUHelpers
9 from soc
.config
.endian
import bigendian
12 class LDSTTestRunner(TestRunner
):
13 def __init__(self
, test_data
):
14 super().__init
__(test_data
, LDSTFunctionUnit
, self
,
15 Function
.LDST
, bigendian
)
17 def get_cu_inputs(self
, dec2
, sim
):
18 """naming (res) must conform to LDSTFunctionUnit input regspec
20 res
= yield from get_cu_inputs(dec2
, sim
)
23 def check_cu_outputs(self
, res
, dec2
, sim
, alu
, code
):
24 """naming (res) must conform to LDSTFunctionUnit output regspec
27 print("check cu outputs", code
, res
)
29 rc
= yield dec2
.e
.do
.rc
.data
30 op
= yield dec2
.e
.do
.insn_type
31 cridx_ok
= yield dec2
.e
.write_cr
.ok
32 cridx
= yield dec2
.e
.write_cr
.data
34 print("check extra output", repr(code
), cridx_ok
, cridx
)
37 self
.assertEqual(cridx_ok
, 1, code
)
38 self
.assertEqual(cridx
, 0, code
)
42 yield from ALUHelpers
.get_sim_int_o(sim_o
, sim
, dec2
)
43 yield from ALUHelpers
.get_sim_int_o1(sim_o
, sim
, dec2
)
44 yield from ALUHelpers
.get_wr_sim_cr_a(sim_o
, sim
, dec2
)
46 ALUHelpers
.check_cr_a(self
, res
, sim_o
, "CR%d %s" % (cridx
, code
))
47 ALUHelpers
.check_int_o(self
, res
, sim_o
, code
)
48 ALUHelpers
.check_int_o1(self
, res
, sim_o
, code
)
54 expected_so
= 1 if sim
.spr
['XER'][XER_bits
['so']] else 0
55 xer_so
= res
['xer_so']
56 self
.assertEqual(expected_so
, xer_so
, code
)
59 if __name__
== "__main__":
60 unittest
.main(exit
=False)
61 suite
= unittest
.TestSuite()
62 suite
.addTest(LDSTTestRunner(LDSTTestCase().test_data
))
64 runner
= unittest
.TextTestRunner()