src/soc/fu/compunits/test/test_logical_compunit.py

   1 import unittest
   2 from soc.decoder.power_enums import (XER_bits, Function)
   3
   4 # XXX bad practice: use of global variables
   5 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase, get_cu_inputs
   6 from soc.fu.logical.test.test_pipe_caller import test_data
   7
   8 from soc.fu.compunits.compunits import LogicalFunctionUnit
   9 from soc.fu.compunits.test.test_compunit import TestRunner
  10
  11
  12 class LogicalTestRunner(TestRunner):
  13     def __init__(self, test_data):
  14         super().__init__(test_data, LogicalFunctionUnit, self,
  15                          Function.LOGICAL)
  16
  17     def get_cu_inputs(self, dec2, sim):
  18         """naming (res) must conform to LogicalFunctionUnit input regspec
  19         """
  20         res = yield from get_cu_inputs(dec2, sim)
  21         return res
  22
  23     def check_cu_outputs(self, res, dec2, sim, code):
  24         """naming (res) must conform to LogicalFunctionUnit output regspec
  25         """
  26
  27         # RT
  28         out_reg_valid = yield dec2.e.write_reg.ok
  29         if out_reg_valid:
  30             write_reg_idx = yield dec2.e.write_reg.data
  31             expected = sim.gpr(write_reg_idx).value
  32             cu_out = res['o']
  33             print(f"expected {expected:x}, actual: {cu_out:x}")
  34             self.assertEqual(expected, cu_out, code)
  35
  36         rc = yield dec2.e.rc.data
  37         op = yield dec2.e.insn_type
  38         cridx_ok = yield dec2.e.write_cr.ok
  39         cridx = yield dec2.e.write_cr.data
  40
  41         print ("check extra output", repr(code), cridx_ok, cridx)
  42
  43         if rc:
  44             self.assertEqual(cridx_ok, 1, code)
  45             self.assertEqual(cridx, 0, code)
  46
  47         # CR (CR0-7)
  48         if cridx_ok:
  49             cr_expected = sim.crl[cridx].get_range().value
  50             cr_actual = res['cr_a']
  51             print ("CR", cridx, cr_expected, cr_actual)
  52             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
  53
  54         # XER.ca
  55         cry_out = yield dec2.e.output_carry
  56         if cry_out:
  57             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  58             xer_ca = res['xer_ca']
  59             real_carry = xer_ca & 0b1 # XXX CO not CO32
  60             self.assertEqual(expected_carry, real_carry, code)
  61             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  62             real_carry32 = bool(xer_ca & 0b10) # XXX CO32
  63             self.assertEqual(expected_carry32, real_carry32, code)
  64
  65
  66 if __name__ == "__main__":
  67     unittest.main(exit=False)
  68     suite = unittest.TestSuite()
  69     suite.addTest(LogicalTestRunner(test_data))
  70
  71     runner = unittest.TextTestRunner()
  72     runner.run(suite)