src/soc/fu/compunits/test/test_logical_compunit.py

   1 import unittest
   2 from soc.decoder.power_enums import (XER_bits, Function)
   3
   4 # XXX bad practice: use of global variables
   5 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
   6 from soc.fu.logical.test.test_pipe_caller import test_data
   7
   8 from soc.fu.compunits.compunits import LogicalFunctionUnit
   9 from soc.fu.compunits.test.test_compunit import TestRunner
  10
  11
  12 class LogicalTestRunner(TestRunner):
  13     def __init__(self, test_data):
  14         super().__init__(test_data, LogicalFunctionUnit, self,
  15                          Function.LOGICAL)
  16
  17     def get_cu_inputs(self, dec2, sim):
  18         """naming (res) must conform to LogicalFunctionUnit input regspec
  19         """
  20         res = {}
  21
  22         # RA (or RC)
  23         reg1_ok = yield dec2.e.read_reg1.ok
  24         if reg1_ok:
  25             data1 = yield dec2.e.read_reg1.data
  26             res['ra'] = sim.gpr(data1).value
  27
  28         # RB (or immediate)
  29         reg2_ok = yield dec2.e.read_reg2.ok
  30         if reg2_ok:
  31             data2 = yield dec2.e.read_reg2.data
  32             res['rb'] = sim.gpr(data2).value
  33
  34         return res
  35
  36     def check_cu_outputs(self, res, dec2, sim, code):
  37         """naming (res) must conform to LogicalFunctionUnit output regspec
  38         """
  39
  40         # RT
  41         out_reg_valid = yield dec2.e.write_reg.ok
  42         if out_reg_valid:
  43             write_reg_idx = yield dec2.e.write_reg.data
  44             expected = sim.gpr(write_reg_idx).value
  45             cu_out = res['o']
  46             print(f"expected {expected:x}, actual: {cu_out:x}")
  47             self.assertEqual(expected, cu_out, code)
  48
  49         rc = yield dec2.e.rc.data
  50         op = yield dec2.e.insn_type
  51         cridx_ok = yield dec2.e.write_cr.ok
  52         cridx = yield dec2.e.write_cr.data
  53
  54         print ("check extra output", repr(code), cridx_ok, cridx)
  55
  56         if rc:
  57             self.assertEqual(cridx_ok, 1, code)
  58             self.assertEqual(cridx, 0, code)
  59
  60         # CR (CR0-7)
  61         if cridx_ok:
  62             cr_expected = sim.crl[cridx].get_range().value
  63             cr_actual = res['cr_a']
  64             print ("CR", cridx, cr_expected, cr_actual)
  65             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
  66
  67         # XER.ca
  68         cry_out = yield dec2.e.output_carry
  69         if cry_out:
  70             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  71             xer_ca = res['xer_ca']
  72             real_carry = xer_ca & 0b1 # XXX CO not CO32
  73             self.assertEqual(expected_carry, real_carry, code)
  74             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  75             real_carry32 = bool(xer_ca & 0b10) # XXX CO32
  76             self.assertEqual(expected_carry32, real_carry32, code)
  77
  78
  79 if __name__ == "__main__":
  80     unittest.main(exit=False)
  81     suite = unittest.TestSuite()
  82     suite.addTest(LogicalTestRunner(test_data))
  83
  84     runner = unittest.TextTestRunner()
  85     runner.run(suite)