src/soc/fu/cr/formal/proof_main_stage.py

   1 # Proof of correctness for partitioned equal signal combiner
   2 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
   3
   4 from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl,
   5                     signed, Array)
   6 from nmigen.asserts import Assert, AnyConst, Assume, Cover
   7 from nmigen.test.utils import FHDLTestCase
   8 from nmigen.cli import rtlil
   9
  10 from soc.fu.cr.main_stage import CRMainStage
  11 from soc.fu.alu.pipe_data import ALUPipeSpec
  12 from soc.fu.alu.alu_input_record import CompALUOpSubset
  13 from soc.decoder.power_enums import InternalOp
  14 import unittest
  15
  16
  17 # This defines a module to drive the device under test and assert
  18 # properties about its outputs
  19 class Driver(Elaboratable):
  20     def __init__(self):
  21         # inputs and outputs
  22         pass
  23
  24     def elaborate(self, platform):
  25         m = Module()
  26         comb = m.d.comb
  27
  28         rec = CompALUOpSubset()
  29         recwidth = 0
  30         # Setup random inputs for dut.op
  31         for p in rec.ports():
  32             width = p.width
  33             recwidth += width
  34             comb += p.eq(AnyConst(width))
  35
  36         pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth)
  37         m.submodules.dut = dut = CRMainStage(pspec)
  38
  39         a = dut.i.a
  40         cr = dut.i.cr
  41         cr_o = dut.o.cr
  42
  43         # setup random inputs
  44         comb += [a.eq(AnyConst(64)),
  45                  cr.eq(AnyConst(64))]
  46
  47         comb += dut.i.ctx.op.eq(rec)
  48
  49         # Assert that op gets copied from the input to output
  50         for rec_sig in rec.ports():
  51             name = rec_sig.name
  52             dut_sig = getattr(dut.o.ctx.op, name)
  53             comb += Assert(dut_sig == rec_sig)
  54
  55         cr_arr = Array([cr[i] for i in range(32)])
  56         cr_o_arr = Array([cr[i] for i in range(32)])
  57
  58         with m.Switch(rec.insn_type):
  59             with m.Case(InternalOp.OP_MTCRF):
  60                 xfx_fields = dut.fields.FormXFX
  61                 FXM = xfx_fields.FXM[0:-1]
  62                 for i in range(8):
  63                     with m.If(FXM[i]):
  64                         comb += Assert(cr_o[4*i:4*i+4] == a[4*i:4*i+4])
  65         return m
  66
  67
  68 class CRTestCase(FHDLTestCase):
  69     def test_formal(self):
  70         module = Driver()
  71         self.assertFormal(module, mode="bmc", depth=2)
  72     def test_ilang(self):
  73         dut = Driver()
  74         vl = rtlil.convert(dut, ports=[])
  75         with open("cr_main_stage.il", "w") as f:
  76             f.write(vl)
  77
  78
  79 if __name__ == '__main__':
  80     unittest.main()