src/soc/fu/cr/main_stage.py

   1 # This stage is intended to do Condition Register instructions
   2 # and output, as well as carry and overflow generation.
   3 # NOTE: with the exception of mtcrf and mfcr, we really should be doing
   4 # the field decoding which
   5 # selects which bits of CR are to be read / written, back in the
   6 # decoder / insn-isue, have both self.i.cr and self.o.cr
   7 # be broken down into 4-bit-wide "registers", with their
   8 # own "Register File" (indexed by bt, ba and bb),
   9 # exactly how INT regs are done (by RA, RB, RS and RT)
  10 # however we are pushed for time so do it as *one* register.
  11
  12 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
  13 from nmutil.pipemodbase import PipeModBase
  14 from soc.fu.cr.pipe_data import CRInputData, CROutputData
  15 from soc.decoder.power_enums import InternalOp
  16
  17 from soc.decoder.power_fields import DecodeFields
  18 from soc.decoder.power_fieldsn import SignalBitRange
  19
  20
  21 class CRMainStage(PipeModBase):
  22     def __init__(self, pspec):
  23         super().__init__(pspec, "main")
  24         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  25         self.fields.create_specs()
  26
  27     def ispec(self):
  28         return CRInputData(self.pspec)
  29
  30     def ospec(self):
  31         return CROutputData(self.pspec)
  32
  33     def elaborate(self, platform):
  34         m = Module()
  35         comb = m.d.comb
  36         op = self.i.ctx.op
  37         a, cr = self.i.a, self.i.cr
  38         xl_fields = self.fields.FormXL
  39         xfx_fields = self.fields.FormXFX
  40         # default: cr_o remains same as cr input unless modified, below
  41         cr_o = Signal.like(cr)
  42         comb += cr_o.eq(cr)
  43
  44         ##### prepare inputs / temp #####
  45
  46         # Generate array for cr input so bits can be selected
  47         cr_arr = Array([Signal(name=f"cr_arr_{i}") for i in range(32)])
  48         for i in range(32):
  49             comb += cr_arr[i].eq(cr[31-i])
  50
  51         # Generate array for cr output so the bit to write to can be
  52         # selected by a signal
  53         cr_out_arr = Array([Signal(name=f"cr_out_{i}") for i in range(32)])
  54         for i in range(32):
  55             comb += cr_o[31-i].eq(cr_out_arr[i])
  56             comb += cr_out_arr[i].eq(cr_arr[i])
  57
  58         # Generate the mask for mtcrf, mtocrf, and mfocrf
  59         # replicate every fxm field in the insn to 4-bit, as a mask
  60         FXM = xfx_fields.FXM[0:-1]
  61         mask = Signal(32, reset_less=True)
  62         comb += mask.eq(Cat(*[Repl(FXM[i], 4) for i in range(8)]))
  63
  64         #################################
  65         ##### main switch statement #####
  66
  67         with m.Switch(op.insn_type):
  68             ##### mcrf #####
  69             with m.Case(InternalOp.OP_MCRF):
  70                 # MCRF copies the 4 bits of crA to crB (for instance
  71                 # copying cr2 to cr1)
  72                 BF = xl_fields.BF[0:-1]   # destination CR
  73                 BFA = xl_fields.BFA[0:-1] # source CR
  74
  75                 for i in range(4):
  76                     comb += cr_out_arr[BF*4 + i].eq(cr_arr[BFA*4 + i])
  77
  78             ##### crand, cror, crnor etc. #####
  79             with m.Case(InternalOp.OP_CROP):
  80                 # crand/cror and friends get decoded to the same opcode, but
  81                 # one of the fields inside the instruction is a 4 bit lookup
  82                 # table. This lookup table gets indexed by bits a and b from
  83                 # the CR to determine what the resulting bit should be.
  84
  85                 # Grab the lookup table for cr_op type instructions
  86                 lut = Array([Signal(name=f"lut{i}") for i in range(4)])
  87                 # There's no field, just have to grab it directly from the insn
  88                 for i in range(4):
  89                     comb += lut[i].eq(op.insn[6+i])
  90
  91                 # Get the bit selector fields from the instruction
  92                 BT = xl_fields.BT[0:-1]
  93                 BA = xl_fields.BA[0:-1]
  94                 BB = xl_fields.BB[0:-1]
  95
  96                 # Use the two input bits to look up the result in the LUT
  97                 comb += cr_out_arr[BT].eq(lut[Cat(cr_arr[BB], cr_arr[BA])])
  98
  99             ##### mtcrf #####
 100             with m.Case(InternalOp.OP_MTCRF):
 101                 # mtocrf and mtcrf are essentially identical
 102                 # put input (RA) - mask-selected - into output CR, leave
 103                 # rest of CR alone.
 104                 comb += cr_o.eq((a[0:32] & mask) | (cr & ~mask))
 105
 106             ##### mfcr #####
 107             with m.Case(InternalOp.OP_MFCR):
 108                 # Ugh. mtocrf and mtcrf have one random bit differentiating
 109                 # them. This bit is not in any particular field, so this
 110                 # extracts that bit from the instruction
 111                 move_one = Signal(reset_less=True)
 112                 comb += move_one.eq(op.insn[20])
 113
 114                 # mfocrf
 115                 with m.If(move_one):
 116                     comb += self.o.o.eq(cr & mask) # output register RT
 117                 # mfcrf
 118                 with m.Else():
 119                     comb += self.o.o.eq(cr)        # output register RT
 120
 121         # output and context
 122         comb += self.o.cr.eq(cr_o)
 123         comb += self.o.ctx.eq(self.i.ctx)
 124
 125         return m