src/soc/fu/cr/main_stage.py

   1 # This stage is intended to do Condition Register instructions
   2 # and output, as well as carry and overflow generation.
   3 # NOTE: with the exception of mtcrf and mfcr, we really should be doing
   4 # the field decoding which
   5 # selects which bits of CR are to be read / written, back in the
   6 # decoder / insn-isue, have both self.i.cr and self.o.cr
   7 # be broken down into 4-bit-wide "registers", with their
   8 # own "Register File" (indexed by bt, ba and bb),
   9 # exactly how INT regs are done (by RA, RB, RS and RT)
  10 # however we are pushed for time so do it as *one* register.
  11
  12 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
  13 from nmutil.pipemodbase import PipeModBase
  14 from soc.fu.cr.pipe_data import CRInputData, CROutputData
  15 from soc.decoder.power_enums import InternalOp
  16
  17 from soc.decoder.power_fields import DecodeFields
  18 from soc.decoder.power_fieldsn import SignalBitRange
  19
  20
  21 class CRMainStage(PipeModBase):
  22     def __init__(self, pspec):
  23         super().__init__(pspec, "main")
  24         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  25         self.fields.create_specs()
  26
  27     def ispec(self):
  28         return CRInputData(self.pspec)
  29
  30     def ospec(self):
  31         return CROutputData(self.pspec)
  32
  33     def elaborate(self, platform):
  34         m = Module()
  35         comb = m.d.comb
  36         op = self.i.ctx.op
  37         a, full_cr = self.i.a, self.i.full_cr
  38         cr_a, cr_b, cr_c = self.i.cr_a, self.i.cr_b, self.i.cr_c
  39         xl_fields = self.fields.FormXL
  40         xfx_fields = self.fields.FormXFX
  41
  42         cr_o = self.o.cr_o
  43
  44         # Generate the mask for mtcrf, mtocrf, and mfocrf
  45         # replicate every fxm field in the insn to 4-bit, as a mask
  46         FXM = xfx_fields.FXM[0:-1]
  47         mask = Signal(32, reset_less=True)
  48         comb += mask.eq(Cat(*[Repl(FXM[i], 4) for i in range(8)]))
  49
  50         # Generate array of bits for cr_a and cr_b
  51         cr_a_arr = Array([cr_a[i] for i in range(4)])
  52         cr_b_arr = Array([cr_b[i] for i in range(4)])
  53         cr_o_arr = Array([cr_o[i] for i in range(4)])
  54
  55         comb += cr_o.eq(cr_c)
  56
  57         with m.Switch(op.insn_type):
  58             ##### mcrf #####
  59             with m.Case(InternalOp.OP_MCRF):
  60                 # MCRF copies the 4 bits of crA to crB (for instance
  61                 # copying cr2 to cr1)
  62                 # Since it takes in a 4 bit cr, and outputs a 4 bit
  63                 # cr, we don't have to do anything special
  64                 comb += cr_o.eq(cr_a)
  65
  66             # ##### crand, cror, crnor etc. #####
  67             with m.Case(InternalOp.OP_CROP):
  68                 # crand/cror and friends get decoded to the same opcode, but
  69                 # one of the fields inside the instruction is a 4 bit lookup
  70                 # table. This lookup table gets indexed by bits a and b from
  71                 # the CR to determine what the resulting bit should be.
  72
  73                 # Grab the lookup table for cr_op type instructions
  74                 lut = Signal(4, reset_less=True)
  75                 # There's no field, just have to grab it directly from the insn
  76                 comb += lut.eq(op.insn[6:10])
  77
  78                 # Get the bit selector fields from the
  79                 # instruction. This operation takes in the little CR
  80                 # bitfields, so these fields need to get truncated to
  81                 # the least significant 2 bits
  82                 BT = xl_fields.BT[0:-1]
  83                 BA = xl_fields.BA[0:-1]
  84                 BB = xl_fields.BB[0:-1]
  85                 bt = Signal(2, reset_less=True)
  86                 ba = Signal(2, reset_less=True)
  87                 bb = Signal(2, reset_less=True)
  88
  89                 # Stupid bit ordering stuff
  90                 comb += bt.eq(3-BT[0:2])
  91                 comb += ba.eq(3-BA[0:2])
  92                 comb += bb.eq(3-BB[0:2])
  93
  94                 # Extract the two input bits from the CRs
  95                 bit_a = Signal(reset_less=True)
  96                 bit_b = Signal(reset_less=True)
  97                 comb += bit_a.eq(cr_a_arr[ba])
  98                 comb += bit_b.eq(cr_b_arr[bb])
  99
 100                 # look up the output bit in the lookup table
 101                 bit_o = Signal()
 102                 comb += bit_o.eq(Mux(bit_b,
 103                                      Mux(bit_a, lut[3], lut[1]),
 104                                      Mux(bit_a, lut[2], lut[0])))
 105
 106                 # insert the output bit into the 4-bit CR output
 107                 comb += cr_o_arr[bt].eq(bit_o)
 108
 109             ##### mtcrf #####
 110             with m.Case(InternalOp.OP_MTCRF):
 111                 # mtocrf and mtcrf are essentially identical
 112                 # put input (RA) - mask-selected - into output CR, leave
 113                 # rest of CR alone.
 114                 comb += self.o.full_cr.eq((a[0:32] & mask) | (full_cr & ~mask))
 115
 116             # ##### mfcr #####
 117             with m.Case(InternalOp.OP_MFCR):
 118                 # Ugh. mtocrf and mtcrf have one random bit differentiating
 119                 # them. This bit is not in any particular field, so this
 120                 # extracts that bit from the instruction
 121                 move_one = Signal(reset_less=True)
 122                 comb += move_one.eq(op.insn[20])
 123
 124                 # mfocrf
 125                 with m.If(move_one):
 126                     # output register RT
 127                     comb += self.o.o.eq(full_cr & mask)
 128                 # mfcrf
 129                 with m.Else():
 130                     # output register RT
 131                     comb += self.o.o.eq(full_cr)
 132
 133         comb += self.o.ctx.eq(self.i.ctx)
 134
 135         return m