3 * https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
5 from nmigen
import Signal
, Const
6 from ieee754
.fpcommon
.getop
import FPPipeContext
7 from soc
.fu
.pipe_data
import IntegerData
, CommonPipeSpec
8 from soc
.fu
.cr
.cr_input_record
import CompCROpSubset
9 from soc
.decoder
.power_decoder2
import Data
12 class CRInputData(IntegerData
):
13 regspec
= [('INT', 'a', '0:63'), # 64 bit range
14 ('INT', 'b', '0:63'), # 6B bit range
15 ('CR', 'full_cr', '0:31'), # 32 bit range
16 ('CR', 'cr_a', '0:3'), # 4 bit range
17 ('CR', 'cr_b', '0:3'), # 4 bit range
18 ('CR', 'cr_c', '0:3')] # 4 bit range
19 def __init__(self
, pspec
):
20 super().__init
__(pspec
)
21 self
.a
= Signal(64, reset_less
=True) # RA
22 self
.b
= Signal(64, reset_less
=True) # RB
23 self
.full_cr
= Signal(32, reset_less
=True) # full CR in
24 self
.cr_a
= Signal(4, reset_less
=True)
25 self
.cr_b
= Signal(4, reset_less
=True)
26 self
.cr_c
= Signal(4, reset_less
=True) # needed for CR_OP partial update
29 yield from super().__iter
__()
39 return lst
+ [self
.a
.eq(i
.a
),
41 self
.full_cr
.eq(i
.full_cr
),
47 class CROutputData(IntegerData
):
48 regspec
= [('INT', 'o', '0:63'), # 64 bit range
49 ('CR', 'full_cr', '0:31'), # 32 bit range
50 ('CR', 'cr_o', '0:3')] # 4 bit range
51 def __init__(self
, pspec
):
52 super().__init
__(pspec
)
53 self
.o
= Data(64, name
="o") # RA
54 self
.full_cr
= Data(32, name
="cr_out") # CR in
55 self
.cr_o
= Data(4, name
="cr_o")
58 yield from super().__iter
__()
65 return lst
+ [self
.o
.eq(i
.o
),
66 self
.full_cr
.eq(i
.full_cr
),
70 class CRPipeSpec(CommonPipeSpec
):
71 regspec
= (CRInputData
.regspec
, CROutputData
.regspec
)
72 opsubsetkls
= CompCROpSubset