src/soc/fu/cr/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.cr.pipeline import CRBasePipe
  16 from soc.fu.alu.alu_input_record import CompALUOpSubset
  17 from soc.fu.cr.pipe_data import CRPipeSpec
  18 import random
  19
  20
  21 class TestCase:
  22     def __init__(self, program, regs, sprs, cr, name):
  23         self.program = program
  24         self.regs = regs
  25         self.sprs = sprs
  26         self.name = name
  27         self.cr = cr
  28
  29
  30 # This test bench is a bit different than is usual. Initially when I
  31 # was writing it, I had all of the tests call a function to create a
  32 # device under test and simulator, initialize the dut, run the
  33 # simulation for ~2 cycles, and assert that the dut output what it
  34 # should have. However, this was really slow, since it needed to
  35 # create and tear down the dut and simulator for every test case.
  36
  37 # Now, instead of doing that, every test case in ALUTestCase puts some
  38 # data into the test_data list below, describing the instructions to
  39 # be tested and the initial state. Once all the tests have been run,
  40 # test_data gets passed to TestRunner which then sets up the DUT and
  41 # simulator once, runs all the data through it, and asserts that the
  42 # results match the pseudocode sim at every cycle.
  43
  44 # By doing this, I've reduced the time it takes to run the test suite
  45 # massively. Before, it took around 1 minute on my computer, now it
  46 # takes around 3 seconds
  47
  48 test_data = []
  49
  50
  51 class CRTestCase(FHDLTestCase):
  52     def __init__(self, name):
  53         super().__init__(name)
  54         self.test_name = name
  55     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={},
  56                         initial_cr=0):
  57         tc = TestCase(prog, initial_regs, initial_sprs, initial_cr,
  58                       self.test_name)
  59         test_data.append(tc)
  60
  61     def test_crop(self):
  62         insns = ["crand", "cror", "crnand", "crnor", "crxor", "creqv",
  63                  "crandc", "crorc"]
  64         for i in range(40):
  65             choice = random.choice(insns)
  66             ba = random.randint(0, 31)
  67             bb = random.randint(0, 31)
  68             bt = random.randint(0, 31)
  69             lst = [f"{choice} {ba}, {bb}, {bt}"]
  70             cr = random.randint(0, (1<<32)-1)
  71             self.run_tst_program(Program(lst), initial_cr=cr)
  72
  73     def test_crand(self):
  74         for i in range(20):
  75             lst = ["crand 0, 11, 13"]
  76             cr = random.randint(0, (1<<32)-1)
  77             self.run_tst_program(Program(lst), initial_cr=cr)
  78
  79     def test_mcrf(self):
  80         lst = ["mcrf 5, 1"]
  81         cr = 0xfeff0000
  82         self.run_tst_program(Program(lst), initial_cr=cr)
  83
  84     def test_mtcrf(self):
  85         for i in range(20):
  86             mask = random.randint(0, 255)
  87             lst = [f"mtcrf {mask}, 2"]
  88             cr = random.randint(0, (1<<32)-1)
  89             initial_regs = [0] * 32
  90             initial_regs[2] = random.randint(0, (1<<32)-1)
  91             self.run_tst_program(Program(lst), initial_regs=initial_regs,
  92                                  initial_cr=cr)
  93     def test_mtocrf(self):
  94         for i in range(20):
  95             mask = 1<<random.randint(0, 7)
  96             lst = [f"mtocrf {mask}, 2"]
  97             cr = random.randint(0, (1<<32)-1)
  98             initial_regs = [0] * 32
  99             initial_regs[2] = random.randint(0, (1<<32)-1)
 100             self.run_tst_program(Program(lst), initial_regs=initial_regs,
 101                                  initial_cr=cr)
 102
 103     def test_mfcr(self):
 104         for i in range(5):
 105             lst = ["mfcr 2"]
 106             cr = random.randint(0, (1<<32)-1)
 107             self.run_tst_program(Program(lst), initial_cr=cr)
 108
 109     def test_mfocrf(self):
 110         for i in range(20):
 111             mask = 1<<random.randint(0, 7)
 112             lst = [f"mfocrf 2, {mask}"]
 113             cr = random.randint(0, (1<<32)-1)
 114             self.run_tst_program(Program(lst), initial_cr=cr)
 115
 116
 117     def test_ilang(self):
 118         pspec = CRPipeSpec(id_wid=2)
 119         alu = CRBasePipe(pspec)
 120         vl = rtlil.convert(alu, ports=alu.ports())
 121         with open("cr_pipeline.il", "w") as f:
 122             f.write(vl)
 123
 124
 125 class TestRunner(FHDLTestCase):
 126     def __init__(self, test_data):
 127         super().__init__("run_all")
 128         self.test_data = test_data
 129
 130     def set_inputs(self, alu, dec2, simulator):
 131         full_reg = yield dec2.e.read_cr_whole
 132
 133         print(simulator.cr.get_range().value)
 134         if full_reg:
 135             yield alu.p.data_i.full_cr.eq(simulator.cr.get_range().value)
 136         else:
 137             cr1_en = yield dec2.e.read_cr1.ok
 138             if cr1_en:
 139                 cr1_sel = yield dec2.e.read_cr1.data
 140                 cr1 = simulator.crl[cr1_sel].get_range().value
 141                 yield alu.p.data_i.cr_a.eq(cr1)
 142             cr2_en = yield dec2.e.read_cr2.ok
 143             if cr2_en:
 144                 cr2_sel = yield dec2.e.read_cr2.data
 145                 cr2 = simulator.crl[cr2_sel].get_range().value
 146                 yield alu.p.data_i.cr_b.eq(cr2)
 147             cr3_en = yield dec2.e.read_cr3.ok
 148             if cr3_en:
 149                 cr3_sel = yield dec2.e.read_cr3.data
 150                 cr3 = simulator.crl[cr3_sel].get_range().value
 151                 yield alu.p.data_i.cr_c.eq(cr3)
 152
 153         reg3_ok = yield dec2.e.read_reg3.ok
 154         if reg3_ok:
 155             reg3_sel = yield dec2.e.read_reg3.data
 156             reg3 = simulator.gpr(reg3_sel).value
 157             yield alu.p.data_i.a.eq(reg3)
 158
 159     def assert_outputs(self, alu, dec2, simulator):
 160         whole_reg = yield dec2.e.write_cr_whole
 161         cr_en = yield dec2.e.write_cr.ok
 162         if whole_reg:
 163             full_cr = yield alu.n.data_o.full_cr.data
 164             expected_cr = simulator.cr.get_range().value
 165             self.assertEqual(expected_cr, full_cr)
 166         elif cr_en:
 167             cr_sel = yield dec2.e.write_cr.data
 168             expected_cr = simulator.crl[cr_sel].get_range().value
 169             real_cr = yield alu.n.data_o.cr_o.data
 170             self.assertEqual(expected_cr, real_cr)
 171
 172
 173     def run_all(self):
 174         m = Module()
 175         comb = m.d.comb
 176         instruction = Signal(32)
 177
 178         pdecode = create_pdecode()
 179
 180         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 181
 182         pspec = CRPipeSpec(id_wid=2)
 183         m.submodules.alu = alu = CRBasePipe(pspec)
 184
 185         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 186         comb += alu.n.ready_i.eq(1)
 187         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 188         sim = Simulator(m)
 189
 190         sim.add_clock(1e-6)
 191         def process():
 192             for test in self.test_data:
 193                 print(test.name)
 194                 program = test.program
 195                 self.subTest(test.name)
 196                 simulator = ISA(pdecode2, test.regs, test.sprs, test.cr)
 197                 gen = program.generate_instructions()
 198                 instructions = list(zip(gen, program.assembly.splitlines()))
 199
 200                 index = simulator.pc.CIA.value//4
 201                 while index < len(instructions):
 202                     ins, code = instructions[index]
 203
 204                     print("0x{:X}".format(ins & 0xffffffff))
 205                     print(code)
 206
 207                     # ask the decoder to decode this binary data (endian'd)
 208                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 209                     yield instruction.eq(ins)          # raw binary instr.
 210                     yield Settle()
 211                     yield from self.set_inputs(alu, pdecode2, simulator)
 212                     yield alu.p.valid_i.eq(1)
 213                     fn_unit = yield pdecode2.e.fn_unit
 214                     self.assertEqual(fn_unit, Function.CR.value, code)
 215                     yield
 216                     opname = code.split(' ')[0]
 217                     yield from simulator.call(opname)
 218                     index = simulator.pc.CIA.value//4
 219
 220                     vld = yield alu.n.valid_o
 221                     while not vld:
 222                         yield
 223                         vld = yield alu.n.valid_o
 224                     yield
 225                     yield from self.assert_outputs(alu, pdecode2, simulator)
 226
 227         sim.add_sync_process(process)
 228         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 229                             traces=[]):
 230             sim.run()
 231     def check_extra_alu_outputs(self, alu, dec2, sim):
 232         rc = yield dec2.e.rc.data
 233         if rc:
 234             cr_expected = sim.crl[0].get_range().value
 235             cr_actual = yield alu.n.data_o.cr0
 236             self.assertEqual(cr_expected, cr_actual)
 237
 238
 239 if __name__ == "__main__":
 240     unittest.main(exit=False)
 241     suite = unittest.TestSuite()
 242     suite.addTest(TestRunner(test_data))
 243
 244     runner = unittest.TextTestRunner()
 245     runner.run(suite)