src/soc/fu/cr/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.cr.pipeline import CRBasePipe
  16 from soc.fu.cr.pipe_data import CRPipeSpec
  17 import random
  18
  19
  20 class TestCase:
  21     def __init__(self, program, regs, sprs, cr, name):
  22         self.program = program
  23         self.regs = regs
  24         self.sprs = sprs
  25         self.name = name
  26         self.cr = cr
  27
  28
  29 # This test bench is a bit different than is usual. Initially when I
  30 # was writing it, I had all of the tests call a function to create a
  31 # device under test and simulator, initialize the dut, run the
  32 # simulation for ~2 cycles, and assert that the dut output what it
  33 # should have. However, this was really slow, since it needed to
  34 # create and tear down the dut and simulator for every test case.
  35
  36 # Now, instead of doing that, every test case in ALUTestCase puts some
  37 # data into the test_data list below, describing the instructions to
  38 # be tested and the initial state. Once all the tests have been run,
  39 # test_data gets passed to TestRunner which then sets up the DUT and
  40 # simulator once, runs all the data through it, and asserts that the
  41 # results match the pseudocode sim at every cycle.
  42
  43 # By doing this, I've reduced the time it takes to run the test suite
  44 # massively. Before, it took around 1 minute on my computer, now it
  45 # takes around 3 seconds
  46
  47 test_data = []
  48
  49
  50 class CRTestCase(FHDLTestCase):
  51     def __init__(self, name):
  52         super().__init__(name)
  53         self.test_name = name
  54
  55     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={},
  56                         initial_cr=0):
  57         tc = TestCase(prog, initial_regs, initial_sprs, initial_cr,
  58                       self.test_name)
  59         test_data.append(tc)
  60
  61     def test_crop(self):
  62         insns = ["crand", "cror", "crnand", "crnor", "crxor", "creqv",
  63                  "crandc", "crorc"]
  64         for i in range(40):
  65             choice = random.choice(insns)
  66             ba = random.randint(0, 31)
  67             bb = random.randint(0, 31)
  68             bt = random.randint(0, 31)
  69             lst = [f"{choice} {ba}, {bb}, {bt}"]
  70             cr = random.randint(0, (1<<32)-1)
  71             self.run_tst_program(Program(lst), initial_cr=cr)
  72
  73     def test_crand(self):
  74         for i in range(20):
  75             lst = ["crand 0, 11, 13"]
  76             cr = random.randint(0, (1<<32)-1)
  77             self.run_tst_program(Program(lst), initial_cr=cr)
  78
  79     def test_mcrf(self):
  80         lst = ["mcrf 5, 1"]
  81         cr = 0xfeff0000
  82         self.run_tst_program(Program(lst), initial_cr=cr)
  83
  84     def test_mtcrf(self):
  85         for i in range(20):
  86             mask = random.randint(0, 255)
  87             lst = [f"mtcrf {mask}, 2"]
  88             cr = random.randint(0, (1<<32)-1)
  89             initial_regs = [0] * 32
  90             initial_regs[2] = random.randint(0, (1<<32)-1)
  91             self.run_tst_program(Program(lst), initial_regs=initial_regs,
  92                                  initial_cr=cr)
  93     def test_mtocrf(self):
  94         for i in range(20):
  95             mask = 1<<random.randint(0, 7)
  96             lst = [f"mtocrf {mask}, 2"]
  97             cr = random.randint(0, (1<<32)-1)
  98             initial_regs = [0] * 32
  99             initial_regs[2] = random.randint(0, (1<<32)-1)
 100             self.run_tst_program(Program(lst), initial_regs=initial_regs,
 101                                  initial_cr=cr)
 102
 103     def test_mfcr(self):
 104         for i in range(5):
 105             lst = ["mfcr 2"]
 106             cr = random.randint(0, (1<<32)-1)
 107             self.run_tst_program(Program(lst), initial_cr=cr)
 108
 109     def test_mfocrf(self):
 110         for i in range(20):
 111             mask = 1<<random.randint(0, 7)
 112             lst = [f"mfocrf 2, {mask}"]
 113             cr = random.randint(0, (1<<32)-1)
 114             self.run_tst_program(Program(lst), initial_cr=cr)
 115
 116     def test_isel(self):
 117         for i in range(20):
 118             bc = random.randint(0, 31)
 119             lst = [f"isel 1, 2, 3, {bc}"]
 120             cr = random.randint(0, (1<<32)-1)
 121             initial_regs = [0] * 32
 122             initial_regs[2] = random.randint(0, (1<<64)-1)
 123             initial_regs[3] = random.randint(0, (1<<64)-1)
 124             self.run_tst_program(Program(lst),
 125                                  initial_regs=initial_regs, initial_cr=cr)
 126
 127     def test_setb(self):
 128         for i in range(20):
 129             bfa = random.randint(0, 7)
 130             lst = [f"setb 1, {bfa}"]
 131             cr = random.randint(0, (1<<32)-1)
 132             self.run_tst_program(Program(lst), initial_cr=cr)
 133
 134
 135
 136     def test_ilang(self):
 137         pspec = CRPipeSpec(id_wid=2)
 138         alu = CRBasePipe(pspec)
 139         vl = rtlil.convert(alu, ports=alu.ports())
 140         with open("cr_pipeline.il", "w") as f:
 141             f.write(vl)
 142
 143
 144 def get_cu_inputs(dec2, sim):
 145     """naming (res) must conform to CRFunctionUnit input regspec
 146     """
 147     res = {}
 148     full_reg = yield dec2.e.read_cr_whole
 149
 150     # full CR
 151     print(sim.cr.get_range().value)
 152     if full_reg:
 153         res['full_cr'] = sim.cr.get_range().value
 154     else:
 155         # CR A
 156         cr1_en = yield dec2.e.read_cr1.ok
 157         if cr1_en:
 158             cr1_sel = yield dec2.e.read_cr1.data
 159             res['cr_a'] = sim.crl[cr1_sel].get_range().value
 160         cr2_en = yield dec2.e.read_cr2.ok
 161         # CR B
 162         if cr2_en:
 163             cr2_sel = yield dec2.e.read_cr2.data
 164             res['cr_b'] = sim.crl[cr2_sel].get_range().value
 165         cr3_en = yield dec2.e.read_cr3.ok
 166         # CR C
 167         if cr3_en:
 168             cr3_sel = yield dec2.e.read_cr3.data
 169             res['cr_c'] = sim.crl[cr3_sel].get_range().value
 170
 171     # RA/RC
 172     reg1_ok = yield dec2.e.read_reg1.ok
 173     if reg1_ok:
 174         data1 = yield dec2.e.read_reg1.data
 175         res['ra'] = sim.gpr(data1).value
 176
 177     # RB (or immediate)
 178     reg2_ok = yield dec2.e.read_reg2.ok
 179     if reg2_ok:
 180         data2 = yield dec2.e.read_reg2.data
 181         res['rb'] = sim.gpr(data2).value
 182
 183     print ("get inputs", res)
 184     return res
 185
 186
 187 class TestRunner(FHDLTestCase):
 188     def __init__(self, test_data):
 189         super().__init__("run_all")
 190         self.test_data = test_data
 191
 192     def set_inputs(self, alu, dec2, simulator):
 193         inp = yield from get_cu_inputs(dec2, simulator)
 194         if 'full_cr' in inp:
 195             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
 196         else:
 197             yield alu.p.data_i.full_cr.eq(0)
 198         if 'cr_a' in inp:
 199             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 200         if 'cr_b' in inp:
 201             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 202         if 'cr_c' in inp:
 203             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 204         if 'ra' in inp:
 205             yield alu.p.data_i.ra.eq(inp['ra'])
 206         else:
 207             yield alu.p.data_i.ra.eq(0)
 208         if 'rb' in inp:
 209             yield alu.p.data_i.rb.eq(inp['rb'])
 210         else:
 211             yield alu.p.data_i.rb.eq(0)
 212
 213     def assert_outputs(self, alu, dec2, simulator, code):
 214         whole_reg = yield dec2.e.write_cr_whole
 215         cr_en = yield dec2.e.write_cr.ok
 216         if whole_reg:
 217             full_cr = yield alu.n.data_o.full_cr.data
 218             expected_cr = simulator.cr.get_range().value
 219             self.assertEqual(expected_cr, full_cr, code)
 220         elif cr_en:
 221             cr_sel = yield dec2.e.write_cr.data
 222             expected_cr = simulator.crl[cr_sel].get_range().value
 223             real_cr = yield alu.n.data_o.cr.data
 224             self.assertEqual(expected_cr, real_cr, code)
 225         alu_out = yield alu.n.data_o.o.data
 226         out_reg_valid = yield dec2.e.write_reg.ok
 227         if out_reg_valid:
 228             write_reg_idx = yield dec2.e.write_reg.data
 229             expected = simulator.gpr(write_reg_idx).value
 230             print(f"expected {expected:x}, actual: {alu_out:x}")
 231             self.assertEqual(expected, alu_out, code)
 232
 233     def run_all(self):
 234         m = Module()
 235         comb = m.d.comb
 236         instruction = Signal(32)
 237
 238         pdecode = create_pdecode()
 239
 240         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 241
 242         pspec = CRPipeSpec(id_wid=2)
 243         m.submodules.alu = alu = CRBasePipe(pspec)
 244
 245         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 246         comb += alu.n.ready_i.eq(1)
 247         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 248         sim = Simulator(m)
 249
 250         sim.add_clock(1e-6)
 251         def process():
 252             for test in self.test_data:
 253                 print(test.name)
 254                 program = test.program
 255                 self.subTest(test.name)
 256                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr)
 257                 gen = program.generate_instructions()
 258                 instructions = list(zip(gen, program.assembly.splitlines()))
 259
 260                 index = sim.pc.CIA.value//4
 261                 while index < len(instructions):
 262                     ins, code = instructions[index]
 263
 264                     print("0x{:X}".format(ins & 0xffffffff))
 265                     print(code)
 266
 267                     # ask the decoder to decode this binary data (endian'd)
 268                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 269                     yield instruction.eq(ins)          # raw binary instr.
 270                     yield Settle()
 271                     yield from self.set_inputs(alu, pdecode2, sim)
 272                     yield alu.p.valid_i.eq(1)
 273                     fn_unit = yield pdecode2.e.fn_unit
 274                     self.assertEqual(fn_unit, Function.CR.value, code)
 275                     yield
 276                     opname = code.split(' ')[0]
 277                     yield from sim.call(opname)
 278                     index = sim.pc.CIA.value//4
 279
 280                     vld = yield alu.n.valid_o
 281                     while not vld:
 282                         yield
 283                         vld = yield alu.n.valid_o
 284                     yield
 285                     yield from self.assert_outputs(alu, pdecode2, sim, code)
 286
 287         sim.add_sync_process(process)
 288         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 289                             traces=[]):
 290             sim.run()
 291
 292
 293 if __name__ == "__main__":
 294     unittest.main(exit=False)
 295     suite = unittest.TestSuite()
 296     suite.addTest(TestRunner(test_data))
 297
 298     runner = unittest.TextTestRunner()
 299     runner.run(suite)