src/soc/fu/cr/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.cr.pipeline import CRBasePipe
  16 from soc.fu.alu.alu_input_record import CompALUOpSubset
  17 from soc.fu.cr.pipe_data import CRPipeSpec
  18 import random
  19
  20
  21 class TestCase:
  22     def __init__(self, program, regs, sprs, cr, name):
  23         self.program = program
  24         self.regs = regs
  25         self.sprs = sprs
  26         self.name = name
  27         self.cr = cr
  28
  29
  30 # This test bench is a bit different than is usual. Initially when I
  31 # was writing it, I had all of the tests call a function to create a
  32 # device under test and simulator, initialize the dut, run the
  33 # simulation for ~2 cycles, and assert that the dut output what it
  34 # should have. However, this was really slow, since it needed to
  35 # create and tear down the dut and simulator for every test case.
  36
  37 # Now, instead of doing that, every test case in ALUTestCase puts some
  38 # data into the test_data list below, describing the instructions to
  39 # be tested and the initial state. Once all the tests have been run,
  40 # test_data gets passed to TestRunner which then sets up the DUT and
  41 # simulator once, runs all the data through it, and asserts that the
  42 # results match the pseudocode sim at every cycle.
  43
  44 # By doing this, I've reduced the time it takes to run the test suite
  45 # massively. Before, it took around 1 minute on my computer, now it
  46 # takes around 3 seconds
  47
  48 test_data = []
  49
  50
  51 class CRTestCase(FHDLTestCase):
  52     def __init__(self, name):
  53         super().__init__(name)
  54         self.test_name = name
  55     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={},
  56                         initial_cr=0):
  57         tc = TestCase(prog, initial_regs, initial_sprs, initial_cr,
  58                       self.test_name)
  59         test_data.append(tc)
  60
  61     def test_crop(self):
  62         insns = ["crand", "cror", "crnand", "crnor", "crxor", "creqv",
  63                  "crandc", "crorc"]
  64         for i in range(40):
  65             choice = random.choice(insns)
  66             ba = random.randint(0, 31)
  67             bb = random.randint(0, 31)
  68             bt = random.randint(0, 31)
  69             lst = [f"{choice} {ba}, {bb}, {bt}"]
  70             cr = random.randint(0, (1<<32)-1)
  71             self.run_tst_program(Program(lst), initial_cr=cr)
  72
  73     def test_crand(self):
  74         for i in range(20):
  75             lst = ["crand 0, 11, 13"]
  76             cr = random.randint(0, (1<<32)-1)
  77             self.run_tst_program(Program(lst), initial_cr=cr)
  78
  79     def test_mcrf(self):
  80         lst = ["mcrf 5, 1"]
  81         cr = 0xfeff0000
  82         self.run_tst_program(Program(lst), initial_cr=cr)
  83
  84     @unittest.skip("broken")
  85     def test_mtcrf(self):
  86         for i in range(20):
  87             mask = random.randint(0, 255)
  88             lst = [f"mtcrf {mask}, 2"]
  89             cr = random.randint(0, (1<<32)-1)
  90             initial_regs = [0] * 32
  91             initial_regs[2] = random.randint(0, (1<<32)-1)
  92             self.run_tst_program(Program(lst), initial_regs=initial_regs,
  93                                  initial_cr=cr)
  94     @unittest.skip("broken")
  95     def test_mtocrf(self):
  96         for i in range(20):
  97             mask = 1<<random.randint(0, 7)
  98             lst = [f"mtocrf {mask}, 2"]
  99             cr = random.randint(0, (1<<32)-1)
 100             initial_regs = [0] * 32
 101             initial_regs[2] = random.randint(0, (1<<32)-1)
 102             self.run_tst_program(Program(lst), initial_regs=initial_regs,
 103                                  initial_cr=cr)
 104
 105     @unittest.skip("broken")
 106     def test_mfcr(self):
 107         for i in range(5):
 108             lst = ["mfcr 2"]
 109             cr = random.randint(0, (1<<32)-1)
 110             self.run_tst_program(Program(lst), initial_cr=cr)
 111
 112     @unittest.skip("broken")
 113     def test_mfocrf(self):
 114         for i in range(20):
 115             mask = 1<<random.randint(0, 7)
 116             lst = [f"mfocrf 2, {mask}"]
 117             cr = random.randint(0, (1<<32)-1)
 118             self.run_tst_program(Program(lst), initial_cr=cr)
 119
 120
 121     def test_ilang(self):
 122         pspec = CRPipeSpec(id_wid=2)
 123         alu = CRBasePipe(pspec)
 124         vl = rtlil.convert(alu, ports=alu.ports())
 125         with open("cr_pipeline.il", "w") as f:
 126             f.write(vl)
 127
 128
 129 class TestRunner(FHDLTestCase):
 130     def __init__(self, test_data):
 131         super().__init__("run_all")
 132         self.test_data = test_data
 133
 134     def set_inputs(self, alu, dec2, simulator):
 135         full_reg = yield dec2.e.read_cr_whole
 136
 137         print(simulator.cr.get_range().value)
 138         if full_reg:
 139             yield alu.p.data_i.full_cr.eq(simulator.cr.get_range().value)
 140         else:
 141             cr1_en = yield dec2.e.read_cr1.ok
 142             if cr1_en:
 143                 cr1_sel = yield dec2.e.read_cr1.data
 144                 cr1 = simulator.crl[cr1_sel].get_range().value
 145                 yield alu.p.data_i.cr_a.eq(cr1)
 146             cr2_en = yield dec2.e.read_cr2.ok
 147             if cr2_en:
 148                 cr2_sel = yield dec2.e.read_cr2.data
 149                 cr2 = simulator.crl[cr2_sel].get_range().value
 150                 yield alu.p.data_i.cr_b.eq(cr2)
 151             cr3_en = yield dec2.e.read_cr3.ok
 152             if cr3_en:
 153                 cr3_sel = yield dec2.e.read_cr3.data
 154                 cr3 = simulator.crl[cr3_sel].get_range().value
 155                 yield alu.p.data_i.cr_c.eq(cr3)
 156
 157         reg3_ok = yield dec2.e.read_reg3.ok
 158         if reg3_ok:
 159             reg3_sel = yield dec2.e.read_reg3.data
 160             reg3 = simulator.gpr(reg3_sel).value
 161             yield alu.p.data_i.a.eq(reg3)
 162
 163     def assert_outputs(self, alu, dec2, simulator):
 164         whole_reg = yield dec2.e.write_cr_whole
 165         cr_en = yield dec2.e.write_cr.ok
 166         if whole_reg:
 167             full_cr = yield alu.n.data_o.full_cr
 168             expected_cr = simulator.cr.get_range().value
 169             self.assertEqual(expected_cr, full_cr)
 170         elif cr_en:
 171             cr_sel = yield dec2.e.write_cr.data
 172             expected_cr = simulator.crl[cr_sel].get_range().value
 173             real_cr = yield alu.n.data_o.cr_o
 174             self.assertEqual(expected_cr, real_cr)
 175
 176
 177     def run_all(self):
 178         m = Module()
 179         comb = m.d.comb
 180         instruction = Signal(32)
 181
 182         pdecode = create_pdecode()
 183
 184         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 185
 186         pspec = CRPipeSpec(id_wid=2)
 187         m.submodules.alu = alu = CRBasePipe(pspec)
 188
 189         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 190         comb += alu.n.ready_i.eq(1)
 191         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 192         sim = Simulator(m)
 193
 194         sim.add_clock(1e-6)
 195         def process():
 196             for test in self.test_data:
 197                 print(test.name)
 198                 program = test.program
 199                 self.subTest(test.name)
 200                 simulator = ISA(pdecode2, test.regs, test.sprs, test.cr)
 201                 gen = program.generate_instructions()
 202                 instructions = list(zip(gen, program.assembly.splitlines()))
 203
 204                 index = simulator.pc.CIA.value//4
 205                 while index < len(instructions):
 206                     ins, code = instructions[index]
 207
 208                     print("0x{:X}".format(ins & 0xffffffff))
 209                     print(code)
 210
 211                     # ask the decoder to decode this binary data (endian'd)
 212                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 213                     yield instruction.eq(ins)          # raw binary instr.
 214                     yield Settle()
 215                     yield from self.set_inputs(alu, pdecode2, simulator)
 216                     yield alu.p.valid_i.eq(1)
 217                     fn_unit = yield pdecode2.e.fn_unit
 218                     self.assertEqual(fn_unit, Function.CR.value, code)
 219                     yield
 220                     opname = code.split(' ')[0]
 221                     yield from simulator.call(opname)
 222                     index = simulator.pc.CIA.value//4
 223
 224                     vld = yield alu.n.valid_o
 225                     while not vld:
 226                         yield
 227                         vld = yield alu.n.valid_o
 228                     yield
 229                     yield from self.assert_outputs(alu, pdecode2, simulator)
 230
 231         sim.add_sync_process(process)
 232         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 233                             traces=[]):
 234             sim.run()
 235     def check_extra_alu_outputs(self, alu, dec2, sim):
 236         rc = yield dec2.e.rc.data
 237         if rc:
 238             cr_expected = sim.crl[0].get_range().value
 239             cr_actual = yield alu.n.data_o.cr0
 240             self.assertEqual(cr_expected, cr_actual)
 241
 242
 243 if __name__ == "__main__":
 244     unittest.main(exit=False)
 245     suite = unittest.TestSuite()
 246     suite.addTest(TestRunner(test_data))
 247
 248     runner = unittest.TextTestRunner()
 249     runner.run(suite)