src/soc/fu/div/core_stages.py

   1 # This stage is the setup stage that converts the inputs
   2 # into the values expected by DivPipeCore
   3
   4 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
   5 from nmutil.pipemodbase import PipeModBase
   6 from soc.fu.logical.pipe_data import LogicalInputData
   7 from soc.fu.alu.pipe_data import ALUOutputData
   8 from ieee754.part.partsig import PartitionedSignal
   9 from soc.decoder.power_enums import InternalOp
  10
  11 from soc.decoder.power_fields import DecodeFields
  12 from soc.decoder.power_fieldsn import SignalBitRange
  13 from soc.fu.div.pipe_data import CoreInputData, CoreInterstageData, CoreOutputData
  14 from ieee754.div_rem_sqrt_rsqrt.core import (DivPipeCoreSetupStage,
  15                                              DivPipeCoreCalculateStage,
  16                                              DivPipeCoreFinalStage)
  17
  18
  19 class DivCoreBaseStage(PipeModBase):
  20     def __init__(self, pspec, modname, core_class, *args, **kwargs):
  21         super().__init__(pspec, modname)
  22         self.core = core_class(pspec.core_config, *args, **kwargs)
  23
  24     def elaborate(self, platform):
  25         m = Module()
  26
  27         m.d.comb += self.o.eq_without_core(self.i)
  28
  29         m.submodules.core = self.core
  30
  31         m.d.comb += self.core.i.eq(self.i.core)
  32         m.d.comb += self.o.core.eq(self.core.o)
  33
  34         return m
  35
  36
  37 class DivCoreSetupStage(DivCoreBaseStage):
  38     def __init__(self, pspec):
  39         super().__init__(pspec, "core_setup_stage", DivPipeCoreSetupStage)
  40
  41     def ispec(self):
  42         return CoreInputData(self.pspec)
  43
  44     def ospec(self):
  45         return CoreInterstageData(self.pspec)
  46
  47
  48 class DivCoreCalculateStage(DivCoreBaseStage):
  49     def __init__(self, pspec, stage_index):
  50         super().__init__(pspec, f"core_calculate_stage_{stage_index}",
  51                          DivPipeCoreCalculateStage, stage_index)
  52
  53     def ispec(self):
  54         return CoreInterstageData(self.pspec)
  55
  56     def ospec(self):
  57         return CoreInterstageData(self.pspec)
  58
  59
  60 class DivCoreFinalStage(DivCoreBaseStage):
  61     def __init__(self, pspec):
  62         super().__init__(pspec, "core_final_stage", DivPipeCoreFinalStage)
  63
  64     def ispec(self):
  65         return CoreInterstageData(self.pspec)
  66
  67     def ospec(self):
  68         return CoreOutputData(self.pspec)