1 from nmigen
import Signal
, Const
2 from soc
.fu
.pipe_data
import IntegerData
3 from soc
.fu
.alu
.pipe_data
import ALUOutputData
, CommonPipeSpec
4 from soc
.fu
.logical
.logical_input_record
import CompLogicalOpSubset
5 from ieee754
.div_rem_sqrt_rsqrt
.core
import (
6 DivPipeCoreConfig
, DivPipeCoreInputData
,
7 DivPipeCoreInterstageData
, DivPipeCoreOutputData
)
10 class DIVInputData(IntegerData
):
11 regspec
= [('INT', 'ra', '0:63'), # RA
12 ('INT', 'rb', '0:63'), # RB/immediate
13 ('XER', 'xer_so', '32'),] # XER bit 32: SO
14 def __init__(self
, pspec
):
15 super().__init
__(pspec
, False)
17 self
.a
, self
.b
= self
.ra
, self
.rb
20 class DIVPipeSpec(CommonPipeSpec
):
21 regspec
= (DIVInputData
.regspec
, ALUOutputData
.regspec
)
22 opsubsetkls
= CompLogicalOpSubset
23 core_config
= DivPipeCoreConfig(
30 class CoreBaseData(DIVInputData
):
31 def __init__(self
, pspec
, core_data_class
):
32 super().__init
__(pspec
)
33 self
.core
= core_data_class(pspec
.core_config
)
34 self
.divisor_neg
= Signal(reset_less
=True)
35 self
.dividend_neg
= Signal(reset_less
=True)
36 self
.div_by_zero
= Signal(reset_less
=True)
38 # set if an overflow for divide extended instructions is detected
39 # because `abs_dividend >= abs_divisor` for the appropriate bit width;
40 # 0 if the instruction is not a divide extended instruction
41 self
.dive_abs_overflow_32
= Signal(reset_less
=True)
42 self
.dive_abs_overflow_64
= Signal(reset_less
=True)
45 yield from super().__iter
__()
46 yield from self
.core
.__iter
__(self
)
47 yield self
.divisor_neg
48 yield self
.dividend_neg
51 return self
.eq_without_core(rhs
) + self
.core
.eq(rhs
.core
)
53 def eq_without_core(self
, rhs
):
54 return super().eq(rhs
) + \
55 [self
.divisor_neg
.eq(rhs
.divisor_neg
),
56 self
.dividend_neg
.eq(rhs
.dividend_neg
)]
59 class CoreInputData(CoreBaseData
):
60 def __init__(self
, pspec
):
61 super().__init
__(pspec
, DivPipeCoreInputData
)
64 class CoreInterstageData(CoreBaseData
):
65 def __init__(self
, pspec
):
66 super().__init
__(pspec
, DivPipeCoreInterstageData
)
69 class CoreOutputData(CoreBaseData
):
70 def __init__(self
, pspec
):
71 super().__init
__(pspec
, DivPipeCoreOutputData
)