src/soc/fu/div/test/helper.py

   1 import random
   2 import unittest
   3 import power_instruction_analyzer as pia
   4 from nmigen import Module, Signal
   5 from nmigen.back.pysim import Simulator, Delay
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.decoder.power_enums import XER_bits, Function
   9 from soc.decoder.isa.all import ISA
  10 from soc.config.endian import bigendian
  11
  12 from soc.fu.test.common import ALUHelpers
  13 from soc.fu.div.pipeline import DivBasePipe
  14 from soc.fu.div.pipe_data import DivPipeSpec
  15
  16
  17 def log_rand(n, min_val=1):
  18     logrange = random.randint(1, n)
  19     return random.randint(min_val, (1 << logrange)-1)
  20
  21
  22 def get_cu_inputs(dec2, sim):
  23     """naming (res) must conform to DivFunctionUnit input regspec
  24     """
  25     res = {}
  26
  27     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2)  # RA
  28     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2)  # RB
  29     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2)  # XER.so
  30
  31     print("alu get_cu_inputs", res)
  32
  33     return res
  34
  35
  36 def pia_res_to_output(pia_res):
  37     retval = {}
  38     if pia_res.rt is not None:
  39         retval["o"] = pia_res.rt
  40     if pia_res.cr0 is not None:
  41         cr0 = pia_res.cr0
  42         v = 0
  43         if cr0.lt:
  44             v |= 8
  45         if cr0.gt:
  46             v |= 4
  47         if cr0.eq:
  48             v |= 2
  49         if cr0.so:
  50             v |= 1
  51         retval["cr_a"] = v
  52     if pia_res.overflow is not None:
  53         overflow = pia_res.overflow
  54         v = 0
  55         if overflow.ov:
  56             v |= 1
  57         if overflow.ov32:
  58             v |= 2
  59         retval["xer_ov"] = v
  60         retval["xer_so"] = overflow.so
  61     else:
  62         retval["xer_ov"] = 0
  63         retval["xer_so"] = 0
  64     return retval
  65
  66
  67 def set_alu_inputs(alu, dec2, sim):
  68     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  69     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  70     # and place it into data_i.b
  71
  72     inp = yield from get_cu_inputs(dec2, sim)
  73     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  74     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  75
  76     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  77
  78     overflow = None
  79     if 'xer_so' not in inp:
  80         return
  81     so = inp['xer_so']
  82
  83     # XXX doesn't work because it's not being properly kept up-to-date
  84     # and we're 2 days before a code-freeze.
  85     # https://bugs.libre-soc.org/show_bug.cgi?id=497
  86     return None
  87
  88     overflow = pia.OverflowFlags(so=bool(so),
  89                                  ov=False,
  90                                  ov32=False)
  91     return pia.InstructionInput(ra=inp["ra"], rb=inp["rb"], rc=0,
  92                                 overflow=overflow)
  93
  94
  95 class DivTestHelper(unittest.TestCase):
  96     def execute(self, alu, instruction, pdecode2, test, div_pipe_kind, sim):
  97         prog = test.program
  98         isa_sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
  99                       test.mem, test.msr,
 100                       bigendian=bigendian)
 101         gen = prog.generate_instructions()
 102         instructions = list(zip(gen, prog.assembly.splitlines()))
 103         yield Delay(0.1e-6)
 104
 105         index = isa_sim.pc.CIA.value//4
 106         while index < len(instructions):
 107             ins, code = instructions[index]
 108
 109             print("instruction: 0x{:X}".format(ins & 0xffffffff))
 110             print(code)
 111             spr = isa_sim.spr
 112             if 'XER' in spr:
 113                 so = 1 if spr['XER'][XER_bits['SO']] else 0
 114                 ov = 1 if spr['XER'][XER_bits['OV']] else 0
 115                 ov32 = 1 if spr['XER'][XER_bits['OV32']] else 0
 116                 print("before: so/ov/32", so, ov, ov32)
 117
 118             # ask the decoder to decode this binary data (endian'd)
 119             # little / big?
 120             yield pdecode2.dec.bigendian.eq(bigendian)
 121             yield instruction.eq(ins)          # raw binary instr.
 122             yield Delay(0.1e-6)
 123             fn_unit = yield pdecode2.e.do.fn_unit
 124             self.assertEqual(fn_unit, Function.DIV.value)
 125             pia_inputs = yield from set_alu_inputs(alu, pdecode2,
 126                                                    isa_sim)
 127
 128             # set valid for one cycle, propagate through pipeline..
 129             # note that it is critically important to do this
 130             # for DIV otherwise it starts trying to produce
 131             # multiple results.
 132             yield alu.p.valid_i.eq(1)
 133             yield
 134             yield alu.p.valid_i.eq(0)
 135
 136             opname = code.split(' ')[0]
 137             fnname = opname.replace(".", "_")
 138             pia_res = None
 139             if pia_inputs:
 140                 print(f"{fnname}({pia_inputs})")
 141                 pia_res = getattr(
 142                     pia, opname.replace(".", "_"))(pia_inputs)
 143                 print(f"-> {pia_res}")
 144
 145             yield from isa_sim.call(opname)
 146             index = isa_sim.pc.CIA.value//4
 147
 148             vld = yield alu.n.valid_o
 149             while not vld:
 150                 yield
 151                 yield Delay(0.1e-6)
 152                 # XXX sim._engine is an internal variable
 153                 # Waiting on https://github.com/nmigen/nmigen/issues/443
 154                 try:
 155                     print(f"time: {sim._engine.now * 1e6}us")
 156                 except AttributeError:
 157                     pass
 158                 vld = yield alu.n.valid_o
 159                 # bug #425 investigation
 160                 do = alu.pipe_end.div_out
 161                 ctx_op = do.i.ctx.op
 162                 is_32bit = yield ctx_op.is_32bit
 163                 is_signed = yield ctx_op.is_signed
 164                 quotient_root = yield do.i.core.quotient_root
 165                 quotient_65 = yield do.quotient_65
 166                 dive_abs_ov32 = yield do.i.dive_abs_ov32
 167                 div_by_zero = yield do.i.div_by_zero
 168                 quotient_neg = yield do.quotient_neg
 169                 print("32bit", hex(is_32bit))
 170                 print("signed", hex(is_signed))
 171                 print("quotient_root", hex(quotient_root))
 172                 print("quotient_65", hex(quotient_65))
 173                 print("div_by_zero", hex(div_by_zero))
 174                 print("dive_abs_ov32", hex(dive_abs_ov32))
 175                 print("quotient_neg", hex(quotient_neg))
 176                 print("vld", vld)
 177                 print("")
 178
 179             yield Delay(0.1e-6)
 180             # XXX sim._engine is an internal variable
 181             # Waiting on https://github.com/nmigen/nmigen/issues/443
 182             try:
 183                 print(f"check time: {sim._engine.now * 1e6}us")
 184             except AttributeError:
 185                 pass
 186             msg = "%s: %s" % (div_pipe_kind.name, code)
 187             msg += " %s" % (repr(prog.assembly))
 188             msg += " %s" % (repr(test.regs))
 189             yield from self.check_alu_outputs(alu, pdecode2,
 190                                               isa_sim, msg,
 191                                               pia_res)
 192             yield
 193
 194     def run_all(self, test_data, div_pipe_kind, file_name_prefix):
 195         m = Module()
 196         comb = m.d.comb
 197         instruction = Signal(32)
 198
 199         pdecode = create_pdecode()
 200
 201         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 202
 203         pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind)
 204         m.submodules.alu = alu = DivBasePipe(pspec)
 205
 206         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 207         comb += alu.n.ready_i.eq(1)
 208         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 209         sim = Simulator(m)
 210
 211         sim.add_clock(1e-6)
 212
 213         def process():
 214             for test in test_data:
 215                 print(test.name)
 216                 with self.subTest(test.name):
 217                     yield from self.execute(alu, instruction, pdecode2,
 218                                             test, div_pipe_kind, sim)
 219
 220         sim.add_sync_process(process)
 221         with sim.write_vcd(f"{file_name_prefix}_{div_pipe_kind.name}.vcd"):
 222             sim.run()
 223
 224     def check_alu_outputs(self, alu, dec2, sim, code, pia_res):
 225
 226         rc = yield dec2.e.do.rc.data
 227         cridx_ok = yield dec2.e.write_cr.ok
 228         cridx = yield dec2.e.write_cr.data
 229
 230         print("check extra output", repr(code), cridx_ok, cridx)
 231         if rc:
 232             self.assertEqual(cridx, 0, code)
 233
 234         sim_o = {}
 235         res = {}
 236
 237         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 238         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
 239         yield from ALUHelpers.get_int_o(res, alu, dec2)
 240         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 241
 242         print("res output", res)
 243
 244         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 245         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 246         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
 247         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 248
 249         print("sim output", sim_o)
 250
 251         print("power-instruction-analyzer result:")
 252         print(pia_res)
 253         if pia_res is not None:
 254             with self.subTest(check="pia", sim_o=sim_o, pia_res=str(pia_res)):
 255                 pia_o = pia_res_to_output(pia_res)
 256                 ALUHelpers.check_int_o(self, res, pia_o, code)
 257                 ALUHelpers.check_cr_a(self, res, pia_o, code)
 258                 ALUHelpers.check_xer_ov(self, res, pia_o, code)
 259                 ALUHelpers.check_xer_so(self, res, pia_o, code)
 260
 261         with self.subTest(check="sim", sim_o=sim_o, pia_res=str(pia_res)):
 262             ALUHelpers.check_int_o(self, res, sim_o, code)
 263             ALUHelpers.check_cr_a(self, res, sim_o, code)
 264             ALUHelpers.check_xer_ov(self, res, sim_o, code)
 265             ALUHelpers.check_xer_so(self, res, sim_o, code)
 266
 267         oe = yield dec2.e.do.oe.oe
 268         oe_ok = yield dec2.e.do.oe.ok
 269         print("oe, oe_ok", oe, oe_ok)
 270         if not oe or not oe_ok:
 271             # if OE not enabled, XER SO and OV must not be activated
 272             so_ok = yield alu.n.data_o.xer_so.ok
 273             ov_ok = yield alu.n.data_o.xer_ov.ok
 274             print("so, ov", so_ok, ov_ok)
 275             self.assertEqual(ov_ok, False, code)
 276             self.assertEqual(so_ok, False, code)