3 from openpower
.simulator
.program
import Program
4 from soc
.config
.endian
import bigendian
6 from soc
.fu
.test
.common
import (TestCase
, TestAccumulatorBase
, skip_case
)
7 from soc
.fu
.div
.pipe_data
import DivPipeKind
9 from soc
.fu
.div
.test
.helper
import (log_rand
, get_cu_inputs
,
10 set_alu_inputs
, DivTestHelper
)
13 class DivTestCases(TestAccumulatorBase
):
14 def case_divdeu_regression(self
):
15 lst
= ["divdeu 3, 1, 2"]
16 initial_regs
= [0] * 32
19 with
Program(lst
, bigendian
) as prog
:
20 self
.add_case(prog
, initial_regs
)
22 def case_divde_regression3(self
):
23 lst
= ["divde 3, 1, 2"]
24 initial_regs
= [0] * 32
25 initial_regs
[1] = 0x8000000000000000
26 initial_regs
[2] = 0xFFFFFFFFFFFFFFFF
27 with
Program(lst
, bigendian
) as prog
:
28 self
.add_case(prog
, initial_regs
)
30 def case_divwe_regression2(self
):
31 lst
= ["divwe 3, 1, 2"]
32 initial_regs
= [0] * 32
33 initial_regs
[1] = 0x80000000
34 initial_regs
[2] = 0xFFFFFFFF
35 with
Program(lst
, bigendian
) as prog
:
36 self
.add_case(prog
, initial_regs
)
38 def case_divde_regression2(self
):
39 lst
= ["divde 3, 1, 2"]
40 initial_regs
= [0] * 32
42 initial_regs
[2] = 0xfffffffffffffffe
43 with
Program(lst
, bigendian
) as prog
:
44 self
.add_case(prog
, initial_regs
)
46 def case_divde_regression(self
):
47 lst
= ["divde 3, 1, 2"]
48 initial_regs
= [0] * 32
50 with
Program(lst
, bigendian
) as prog
:
51 self
.add_case(prog
, initial_regs
)
53 def case_moduw_regression(self
):
54 lst
= ["moduw 3, 1, 2"]
55 initial_regs
= [0] * 32
57 initial_regs
[2] = 0xffffffffffffffff
58 with
Program(lst
, bigendian
) as prog
:
59 self
.add_case(prog
, initial_regs
)
61 def case_modsw_regression(self
):
62 lst
= ["modsw 3, 1, 2"]
63 initial_regs
= [0] * 32
64 initial_regs
[1] = 0xffffffffffffffff
66 with
Program(lst
, bigendian
) as prog
:
67 self
.add_case(prog
, initial_regs
)
69 def case_divweu_regression(self
):
70 # simulator is wrong, FSM and power-instruction-analyzer both correct
71 lst
= ["divweu 3, 1, 2"]
72 initial_regs
= [0] * 32
74 initial_regs
[2] = 0xffffffffffffffff
75 with
Program(lst
, bigendian
) as prog
:
76 self
.add_case(prog
, initial_regs
)
78 def case_divwe_regression(self
):
79 # div FU and power-instruction-analyzer both correctly return 0
80 # hitting behavior undefined by Power v3.1 spec, need to adjust
81 # simulator API to tell tests that the simulator's output doesn't
82 # need to completely match
83 lst
= [f
"divwe 3, 1, 2"]
84 initial_regs
= [0] * 32
87 with
Program(lst
, bigendian
) as prog
:
88 self
.add_case(prog
, initial_regs
)
90 def case_divwe__regression(self
):
91 lst
= ["divwe. 3, 1, 2"]
92 initial_regs
= [0] * 32
93 with
Program(lst
, bigendian
) as prog
:
94 self
.add_case(prog
, initial_regs
)
96 def case_divw_regression(self
):
97 # simulator is wrong, FSM and power-instruction-analyzer both correct
98 lst
= [f
"divw 0, 1, 2"]
99 initial_regs
= [0] * 32
100 initial_regs
[2] = 0x2
101 initial_regs
[1] = 0x80000000
102 with
Program(lst
, bigendian
) as prog
:
103 self
.add_case(prog
, initial_regs
)
106 def case_modsd_regression2(self
):
107 lst
= [f
"modsd 0, 1, 2"]
108 initial_regs
= [0] * 32
109 initial_regs
[2] = 0xff
110 initial_regs
[1] = 0x7fffffffffffffff
111 with
Program(lst
, bigendian
) as prog
:
112 self
.add_case(prog
, initial_regs
)
115 def case_modsd_regression(self
):
116 lst
= [f
"modsd 17, 27, 0"]
117 initial_regs
= [0] * 32
118 initial_regs
[0] = 0xff
119 initial_regs
[27] = 0x7fffffffffffffff
120 with
Program(lst
, bigendian
) as prog
:
121 self
.add_case(prog
, initial_regs
)
123 def case_divduo_regression(self
):
124 lst
= [f
"divduo. 11, 20, 6"]
125 initial_regs
= [0] * 32
126 # gpr: 00ff00ff00ff0080 <- r6
127 # gpr: 000000000000007f <- r11
128 # gpr: 7f6e5d4c3b2a1908 <- r20
129 initial_regs
[6] = 0x00ff00ff00ff0080
130 initial_regs
[20] = 0x7f6e5d4c3b2a1908
131 with
Program(lst
, bigendian
) as prog
:
132 self
.add_case(prog
, initial_regs
)
134 def case_0_regression(self
):
136 lst
= ["divwo 3, 1, 2"]
137 initial_regs
= [0] * 32
138 initial_regs
[1] = 0xbc716835f32ac00c
139 initial_regs
[2] = 0xcdf69a7f7042db66
140 with
Program(lst
, bigendian
) as prog
:
141 self
.add_case(prog
, initial_regs
)
143 def case_1_regression(self
):
144 lst
= ["divwo 3, 1, 2"]
145 initial_regs
= [0] * 32
146 initial_regs
[1] = 0x10000000000000000-4
147 initial_regs
[2] = 0x10000000000000000-2
148 with
Program(lst
, bigendian
) as prog
:
149 self
.add_case(prog
, initial_regs
)
151 def case_2_regression(self
):
152 lst
= ["divwo 3, 1, 2"]
153 initial_regs
= [0] * 32
154 initial_regs
[1] = 0xffffffffffff9321
155 initial_regs
[2] = 0xffffffffffff7012
156 with
Program(lst
, bigendian
) as prog
:
157 self
.add_case(prog
, initial_regs
)
159 def case_3_regression(self
):
160 lst
= ["divwo. 3, 1, 2"]
161 initial_regs
= [0] * 32
162 initial_regs
[1] = 0x1b8e32f2458746af
163 initial_regs
[2] = 0x6b8aee2ccf7d62e9
164 with
Program(lst
, bigendian
) as prog
:
165 self
.add_case(prog
, initial_regs
)
167 def case_4_regression(self
):
168 lst
= ["divw 3, 1, 2"]
169 initial_regs
= [0] * 32
170 initial_regs
[1] = 0x1c4e6c2f3aa4a05c
171 initial_regs
[2] = 0xe730c2eed6cc8dd7
172 with
Program(lst
, bigendian
) as prog
:
173 self
.add_case(prog
, initial_regs
)
175 def case_5_regression(self
):
176 lst
= ["divw 3, 1, 2",
178 initial_regs
= [0] * 32
179 initial_regs
[1] = 0x1c4e6c2f3aa4a05c
180 initial_regs
[2] = 0xe730c2eed6cc8dd7
181 initial_regs
[4] = 0x1b8e32f2458746af
182 initial_regs
[5] = 0x6b8aee2ccf7d62e9
183 with
Program(lst
, bigendian
) as prog
:
184 self
.add_case(prog
, initial_regs
)
186 def case_6_regression(self
):
187 # CR0 not getting set properly for this one
188 # turns out that overflow is not set correctly in
189 # fu/div/output_stage.py calc_overflow
190 # https://bugs.libre-soc.org/show_bug.cgi?id=425
191 lst
= ["divw. 3, 1, 2"]
192 initial_regs
= [0] * 32
193 initial_regs
[1] = 0x61c1cc3b80f2a6af
194 initial_regs
[2] = 0x9dc66a7622c32bc0
195 with
Program(lst
, bigendian
) as prog
:
196 self
.add_case(prog
, initial_regs
)
198 def case_7_regression(self
):
199 # https://bugs.libre-soc.org/show_bug.cgi?id=425
200 lst
= ["divw. 3, 1, 2"]
201 initial_regs
= [0] * 32
202 initial_regs
[1] = 0xf1791627e05e8096
203 initial_regs
[2] = 0xffc868bf4573da0b
204 with
Program(lst
, bigendian
) as prog
:
205 self
.add_case(prog
, initial_regs
)
207 def case_8_fsm_regression(self
): # FSM result is "36" not 6
208 lst
= ["divwu. 3, 1, 2"]
209 initial_regs
= [0] * 32
212 with
Program(lst
, bigendian
) as prog
:
213 self
.add_case(prog
, initial_regs
)
215 def case_9_regression(self
): # CR0 fails: expected 0b10, actual 0b11
216 lst
= ["divw. 3, 1, 2"]
217 initial_regs
= [0] * 32
220 with
Program(lst
, bigendian
) as prog
:
221 self
.add_case(prog
, initial_regs
)
223 def case_10_regression(self
): # overflow fails
224 lst
= ["divwo 3, 1, 2"]
225 initial_regs
= [0] * 32
226 initial_regs
[1] = 0xbc716835f32ac00c
227 initial_regs
[2] = 0xcdf69a7f7042db66
228 with
Program(lst
, bigendian
) as prog
:
229 self
.add_case(prog
, initial_regs
)
231 def case_11_regression(self
):
232 lst
= ["divwo. 3, 1, 2"]
233 initial_regs
= [0] * 32
234 initial_regs
[1] = 0xffffffffffffffff
235 initial_regs
[2] = 0xffffffffffffffff
236 with
Program(lst
, bigendian
) as prog
:
237 self
.add_case(prog
, initial_regs
)
239 def case_divw_by_zero_1(self
):
240 lst
= ["divw. 3, 1, 2"]
241 initial_regs
= [0] * 32
242 initial_regs
[1] = 0x1
243 initial_regs
[2] = 0x0
244 with
Program(lst
, bigendian
) as prog
:
245 self
.add_case(prog
, initial_regs
)
247 def case_divw_overflow2(self
):
248 lst
= ["divw. 3, 1, 2"]
249 initial_regs
= [0] * 32
250 initial_regs
[1] = 0x80000000
251 initial_regs
[2] = 0xffffffffffffffff # top bits don't seem to matter
252 with
Program(lst
, bigendian
) as prog
:
253 self
.add_case(prog
, initial_regs
)
255 def case_divw_overflow3(self
):
256 lst
= ["divw. 3, 1, 2"]
257 initial_regs
= [0] * 32
258 initial_regs
[1] = 0x80000000
259 initial_regs
[2] = 0xffffffff
260 with
Program(lst
, bigendian
) as prog
:
261 self
.add_case(prog
, initial_regs
)
263 def case_divwuo_regression_1(self
):
264 lst
= ["divwuo. 3, 1, 2"]
265 initial_regs
= [0] * 32
266 initial_regs
[1] = 0x7591a398c4e32b68
267 initial_regs
[2] = 0x48674ab432867d69
268 with
Program(lst
, bigendian
) as prog
:
269 self
.add_case(prog
, initial_regs
)
271 def case_divwuo_1(self
):
272 lst
= ["divwuo. 3, 1, 2"]
273 initial_regs
= [0] * 32
274 initial_regs
[1] = 0x50
275 initial_regs
[2] = 0x2
276 with
Program(lst
, bigendian
) as prog
:
277 self
.add_case(prog
, initial_regs
)
279 def case_rand_divwu(self
):
280 insns
= ["divwu", "divwu.", "divwuo", "divwuo."]
282 choice
= random
.choice(insns
)
283 lst
= [f
"{choice} 3, 1, 2"]
284 initial_regs
= [0] * 32
285 initial_regs
[1] = log_rand(32)
286 initial_regs
[2] = log_rand(32)
287 with
Program(lst
, bigendian
) as prog
:
288 self
.add_case(prog
, initial_regs
)
290 def case_rand_divw(self
):
291 insns
= ["divw", "divw.", "divwo", "divwo."]
293 choice
= random
.choice(insns
)
294 lst
= [f
"{choice} 3, 1, 2"]
295 initial_regs
= [0] * 32
296 initial_regs
[1] = log_rand(32)
297 initial_regs
[2] = log_rand(32)
298 with
Program(lst
, bigendian
) as prog
:
299 self
.add_case(prog
, initial_regs
)
302 class TestPipe(DivTestHelper
):
303 def test_div_pipe_core(self
):
304 self
.run_all(DivTestCases().test_data
,
305 DivPipeKind
.DivPipeCore
, "div_pipe_caller")
307 def test_fsm_div_core(self
):
308 self
.run_all(DivTestCases().test_data
,
309 DivPipeKind
.FSMDivCore
, "div_pipe_caller")
311 def test_sim_only(self
):
312 self
.run_all(DivTestCases().test_data
,
313 DivPipeKind
.SimOnly
, "div_pipe_caller")
316 if __name__
== "__main__":