src/soc/fu/div/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import (TestCase, ALUHelpers)
  16 from soc.fu.div.pipeline import DIVBasePipe
  17 from soc.fu.div.pipe_data import DIVPipeSpec
  18 import random
  19
  20
  21 def get_cu_inputs(dec2, sim):
  22     """naming (res) must conform to DIVFunctionUnit input regspec
  23     """
  24     res = {}
  25
  26     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
  27     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
  28     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
  29
  30     print ("alu get_cu_inputs", res)
  31
  32     return res
  33
  34
  35
  36 def set_alu_inputs(alu, dec2, sim):
  37     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  38     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  39     # and place it into data_i.b
  40
  41     inp = yield from get_cu_inputs(dec2, sim)
  42     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  43     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  44
  45     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  46
  47
  48 # This test bench is a bit different than is usual. Initially when I
  49 # was writing it, I had all of the tests call a function to create a
  50 # device under test and simulator, initialize the dut, run the
  51 # simulation for ~2 cycles, and assert that the dut output what it
  52 # should have. However, this was really slow, since it needed to
  53 # create and tear down the dut and simulator for every test case.
  54
  55 # Now, instead of doing that, every test case in DIVTestCase puts some
  56 # data into the test_data list below, describing the instructions to
  57 # be tested and the initial state. Once all the tests have been run,
  58 # test_data gets passed to TestRunner which then sets up the DUT and
  59 # simulator once, runs all the data through it, and asserts that the
  60 # results match the pseudocode sim at every cycle.
  61
  62 # By doing this, I've reduced the time it takes to run the test suite
  63 # massively. Before, it took around 1 minute on my computer, now it
  64 # takes around 3 seconds
  65
  66
  67 class DIVTestCase(FHDLTestCase):
  68     test_data = []
  69
  70     def __init__(self, name):
  71         super().__init__(name)
  72         self.test_name = name
  73
  74     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  75         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  76         self.test_data.append(tc)
  77
  78     def test_0_regression(self):
  79         for i in range(40):
  80             lst = ["divwo 3, 1, 2"]
  81             initial_regs = [0] * 32
  82             initial_regs[1] = 0xbc716835f32ac00c
  83             initial_regs[2] = 0xcdf69a7f7042db66
  84             self.run_tst_program(Program(lst), initial_regs)
  85
  86     def test_0_regression(self):
  87         for i in range(40):
  88             lst = ["divwo 3, 1, 2"]
  89             initial_regs = [0] * 32
  90             initial_regs[1] = 0x10000000000000000-4
  91             initial_regs[2] = 0x10000000000000000-2
  92             self.run_tst_program(Program(lst), initial_regs)
  93
  94     def test_0_regression(self):
  95         for i in range(40):
  96             lst = ["divwo 3, 1, 2"]
  97             initial_regs = [0] * 32
  98             initial_regs[1] = 0xffffffffffff9321
  99             initial_regs[2] = 0xffffffffffff7012
 100             self.run_tst_program(Program(lst), initial_regs)
 101
 102     def test_rand_divw(self):
 103         insns = ["divw", "divw.", "divwo", "divwo."]
 104         for i in range(40):
 105             choice = random.choice(insns)
 106             lst = [f"{choice} 3, 1, 2"]
 107             initial_regs = [0] * 32
 108             initial_regs[1] = random.randint(0, (1<<64)-1)
 109             initial_regs[2] = random.randint(0, (1<<64)-1)
 110             self.run_tst_program(Program(lst), initial_regs)
 111
 112     def test_ilang(self):
 113         pspec = DIVPipeSpec(id_wid=2)
 114         alu = DIVBasePipe(pspec)
 115         vl = rtlil.convert(alu, ports=alu.ports())
 116         with open("alu_pipeline.il", "w") as f:
 117             f.write(vl)
 118
 119
 120 class TestRunner(FHDLTestCase):
 121     def __init__(self, test_data):
 122         super().__init__("run_all")
 123         self.test_data = test_data
 124
 125     def run_all(self):
 126         m = Module()
 127         comb = m.d.comb
 128         instruction = Signal(32)
 129
 130         pdecode = create_pdecode()
 131
 132         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 133
 134         pspec = DIVPipeSpec(id_wid=2)
 135         m.submodules.alu = alu = DIVBasePipe(pspec)
 136
 137         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 138         comb += alu.p.valid_i.eq(1)
 139         comb += alu.n.ready_i.eq(1)
 140         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 141         sim = Simulator(m)
 142
 143         sim.add_clock(1e-6)
 144         def process():
 145             for test in self.test_data:
 146                 print(test.name)
 147                 program = test.program
 148                 self.subTest(test.name)
 149                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
 150                                 test.mem, test.msr)
 151                 gen = program.generate_instructions()
 152                 instructions = list(zip(gen, program.assembly.splitlines()))
 153
 154                 index = sim.pc.CIA.value//4
 155                 while index < len(instructions):
 156                     ins, code = instructions[index]
 157
 158                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 159                     print(code)
 160                     if 'XER' in sim.spr:
 161                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 162                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 163                         ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 164                         print ("before: so/ov/32", so, ov, ov32)
 165
 166                     # ask the decoder to decode this binary data (endian'd)
 167                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 168                     yield instruction.eq(ins)          # raw binary instr.
 169                     yield Settle()
 170                     fn_unit = yield pdecode2.e.do.fn_unit
 171                     self.assertEqual(fn_unit, Function.DIV.value)
 172                     yield from set_alu_inputs(alu, pdecode2, sim)
 173                     yield
 174                     opname = code.split(' ')[0]
 175                     yield from sim.call(opname)
 176                     index = sim.pc.CIA.value//4
 177
 178                     vld = yield alu.n.valid_o
 179                     while not vld:
 180                         yield
 181                         vld = yield alu.n.valid_o
 182                     yield
 183
 184                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 185
 186         sim.add_sync_process(process)
 187         with sim.write_vcd("div_simulator.vcd", "div_simulator.gtkw",
 188                             traces=[]):
 189             sim.run()
 190
 191     def check_alu_outputs(self, alu, dec2, sim, code):
 192
 193         rc = yield dec2.e.do.rc.data
 194         cridx_ok = yield dec2.e.write_cr.ok
 195         cridx = yield dec2.e.write_cr.data
 196
 197         print ("check extra output", repr(code), cridx_ok, cridx)
 198         if rc:
 199             self.assertEqual(cridx, 0, code)
 200
 201         oe = yield dec2.e.do.oe.oe
 202         oe_ok = yield dec2.e.do.oe.ok
 203         if not oe or not oe_ok:
 204             # if OE not enabled, XER SO and OV must correspondingly be false
 205             so_ok = yield alu.n.data_o.xer_so.ok
 206             ov_ok = yield alu.n.data_o.xer_ov.ok
 207             self.assertEqual(so_ok, False, code)
 208             self.assertEqual(ov_ok, False, code)
 209
 210         sim_o = {}
 211         res = {}
 212
 213         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 214         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
 215         yield from ALUHelpers.get_int_o(res, alu, dec2)
 216         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 217
 218         print ("res output", res)
 219
 220         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 221         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 222         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
 223         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 224
 225         print ("sim output", sim_o)
 226
 227         ALUHelpers.check_int_o(self, res, sim_o, code)
 228         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 229         ALUHelpers.check_xer_ov(self, res, sim_o, code)
 230         ALUHelpers.check_xer_so(self, res, sim_o, code)
 231
 232
 233 if __name__ == "__main__":
 234     unittest.main(exit=False)
 235     suite = unittest.TestSuite()
 236     suite.addTest(TestRunner(DIVTestCase.test_data))
 237
 238     runner = unittest.TextTestRunner()
 239     runner.run(suite)