3 from nmigen
import Module
, Signal
4 from nmigen
.back
.pysim
import Simulator
, Delay
5 from nmigen
.cli
import rtlil
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.decoder
.power_enums
import XER_bits
, Function
9 from soc
.simulator
.program
import Program
10 from soc
.decoder
.isa
.all
import ISA
11 from soc
.config
.endian
import bigendian
13 from soc
.fu
.test
.common
import (TestCase
, ALUHelpers
)
14 from soc
.fu
.div
.pipeline
import DivBasePipe
15 from soc
.fu
.div
.pipe_data
import DivPipeSpec
, DivPipeKind
18 def log_rand(n
, min_val
=1):
19 logrange
= random
.randint(1, n
)
20 return random
.randint(min_val
, (1 << logrange
)-1)
23 def get_cu_inputs(dec2
, sim
):
24 """naming (res) must conform to DivFunctionUnit input regspec
28 yield from ALUHelpers
.get_sim_int_ra(res
, sim
, dec2
) # RA
29 yield from ALUHelpers
.get_sim_int_rb(res
, sim
, dec2
) # RB
30 yield from ALUHelpers
.get_sim_xer_so(res
, sim
, dec2
) # XER.so
32 print("alu get_cu_inputs", res
)
37 def set_alu_inputs(alu
, dec2
, sim
):
38 # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
39 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
40 # and place it into data_i.b
42 inp
= yield from get_cu_inputs(dec2
, sim
)
43 yield from ALUHelpers
.set_int_ra(alu
, dec2
, inp
)
44 yield from ALUHelpers
.set_int_rb(alu
, dec2
, inp
)
46 yield from ALUHelpers
.set_xer_so(alu
, dec2
, inp
)
49 # This test bench is a bit different than is usual. Initially when I
50 # was writing it, I had all of the tests call a function to create a
51 # device under test and simulator, initialize the dut, run the
52 # simulation for ~2 cycles, and assert that the dut output what it
53 # should have. However, this was really slow, since it needed to
54 # create and tear down the dut and simulator for every test case.
56 # Now, instead of doing that, every test case in DivTestCase puts some
57 # data into the test_data list below, describing the instructions to
58 # be tested and the initial state. Once all the tests have been run,
59 # test_data gets passed to TestRunner which then sets up the DUT and
60 # simulator once, runs all the data through it, and asserts that the
61 # results match the pseudocode sim at every cycle.
63 # By doing this, I've reduced the time it takes to run the test suite
64 # massively. Before, it took around 1 minute on my computer, now it
65 # takes around 3 seconds
71 for n
, v
in self
.__class
__.__dict
__.items():
72 if n
.startswith("test") and callable(v
):
73 self
._current
_test
_name
= n
76 def run_test_program(self
, prog
, initial_regs
=None, initial_sprs
=None):
77 tc
= TestCase(prog
, self
._current
_test
_name
,
78 initial_regs
, initial_sprs
)
79 self
.test_data
.append(tc
)
81 def test_0_regression(self
):
83 lst
= ["divwo 3, 1, 2"]
84 initial_regs
= [0] * 32
85 initial_regs
[1] = 0xbc716835f32ac00c
86 initial_regs
[2] = 0xcdf69a7f7042db66
87 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
89 def test_1_regression(self
):
90 lst
= ["divwo 3, 1, 2"]
91 initial_regs
= [0] * 32
92 initial_regs
[1] = 0x10000000000000000-4
93 initial_regs
[2] = 0x10000000000000000-2
94 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
96 def test_2_regression(self
):
97 lst
= ["divwo 3, 1, 2"]
98 initial_regs
= [0] * 32
99 initial_regs
[1] = 0xffffffffffff9321
100 initial_regs
[2] = 0xffffffffffff7012
101 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
103 def test_3_regression(self
):
104 lst
= ["divwo. 3, 1, 2"]
105 initial_regs
= [0] * 32
106 initial_regs
[1] = 0x1b8e32f2458746af
107 initial_regs
[2] = 0x6b8aee2ccf7d62e9
108 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
110 def test_4_regression(self
):
111 lst
= ["divw 3, 1, 2"]
112 initial_regs
= [0] * 32
113 initial_regs
[1] = 0x1c4e6c2f3aa4a05c
114 initial_regs
[2] = 0xe730c2eed6cc8dd7
115 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
117 def test_5_regression(self
):
118 lst
= ["divw 3, 1, 2",
120 initial_regs
= [0] * 32
121 initial_regs
[1] = 0x1c4e6c2f3aa4a05c
122 initial_regs
[2] = 0xe730c2eed6cc8dd7
123 initial_regs
[4] = 0x1b8e32f2458746af
124 initial_regs
[5] = 0x6b8aee2ccf7d62e9
125 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
127 def test_6_regression(self
):
128 # CR0 not getting set properly for this one
129 # turns out that overflow is not set correctly in
130 # fu/div/output_stage.py calc_overflow
131 # https://bugs.libre-soc.org/show_bug.cgi?id=425
132 lst
= ["divw. 3, 1, 2"]
133 initial_regs
= [0] * 32
134 initial_regs
[1] = 0x61c1cc3b80f2a6af
135 initial_regs
[2] = 0x9dc66a7622c32bc0
136 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
138 def test_7_regression(self
):
139 # https://bugs.libre-soc.org/show_bug.cgi?id=425
140 lst
= ["divw. 3, 1, 2"]
141 initial_regs
= [0] * 32
142 initial_regs
[1] = 0xf1791627e05e8096
143 initial_regs
[2] = 0xffc868bf4573da0b
144 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
146 def test_divw_by_zero_1(self
):
147 lst
= ["divw. 3, 1, 2"]
148 initial_regs
= [0] * 32
149 initial_regs
[1] = 0x1
150 initial_regs
[2] = 0x0
151 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
153 def test_divw_overflow2(self
):
154 lst
= ["divw. 3, 1, 2"]
155 initial_regs
= [0] * 32
156 initial_regs
[1] = 0x80000000
157 initial_regs
[2] = 0xffffffffffffffff # top bits don't seem to matter
158 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
160 def test_divw_overflow3(self
):
161 lst
= ["divw. 3, 1, 2"]
162 initial_regs
= [0] * 32
163 initial_regs
[1] = 0x80000000
164 initial_regs
[2] = 0xffffffff
165 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
167 def test_divwuo_regression_1(self
):
168 lst
= ["divwuo. 3, 1, 2"]
169 initial_regs
= [0] * 32
170 initial_regs
[1] = 0x7591a398c4e32b68
171 initial_regs
[2] = 0x48674ab432867d69
172 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
174 def test_divwuo_1(self
):
175 lst
= ["divwuo. 3, 1, 2"]
176 initial_regs
= [0] * 32
177 initial_regs
[1] = 0x50
178 initial_regs
[2] = 0x2
179 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
181 def test_rand_divwu(self
):
182 insns
= ["divwu", "divwu.", "divwuo", "divwuo."]
184 choice
= random
.choice(insns
)
185 lst
= [f
"{choice} 3, 1, 2"]
186 initial_regs
= [0] * 32
187 initial_regs
[1] = log_rand(32)
188 initial_regs
[2] = log_rand(32)
189 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
191 def test_rand_divw(self
):
192 insns
= ["divw", "divw.", "divwo", "divwo."]
194 choice
= random
.choice(insns
)
195 lst
= [f
"{choice} 3, 1, 2"]
196 initial_regs
= [0] * 32
197 initial_regs
[1] = log_rand(32)
198 initial_regs
[2] = log_rand(32)
199 self
.run_test_program(Program(lst
, bigendian
), initial_regs
)
202 class TestRunner(unittest
.TestCase
):
203 def write_ilang(self
, div_pipe_kind
):
204 pspec
= DivPipeSpec(id_wid
=2, div_pipe_kind
=div_pipe_kind
)
205 alu
= DivBasePipe(pspec
)
206 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
207 with
open(f
"div_pipeline_{div_pipe_kind.name}.il", "w") as f
:
210 def test_write_ilang_div_pipe_core(self
):
211 self
.write_ilang(DivPipeKind
.DivPipeCore
)
213 def test_write_ilang_fsm_div_core(self
):
214 self
.write_ilang(DivPipeKind
.FSMDivCore
)
216 def test_write_ilang_sim_only(self
):
217 self
.write_ilang(DivPipeKind
.SimOnly
)
219 def run_all(self
, div_pipe_kind
):
220 test_data
= DivTestCases().test_data
223 instruction
= Signal(32)
225 pdecode
= create_pdecode()
227 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
229 pspec
= DivPipeSpec(id_wid
=2, div_pipe_kind
=div_pipe_kind
)
230 m
.submodules
.alu
= alu
= DivBasePipe(pspec
)
232 comb
+= alu
.p
.data_i
.ctx
.op
.eq_from_execute1(pdecode2
.e
)
233 comb
+= alu
.n
.ready_i
.eq(1)
234 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
240 for test
in test_data
:
243 with self
.subTest(test
.name
):
244 isa_sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
,
247 gen
= prog
.generate_instructions()
248 instructions
= list(zip(gen
, prog
.assembly
.splitlines()))
251 index
= isa_sim
.pc
.CIA
.value
//4
252 while index
< len(instructions
):
253 ins
, code
= instructions
[index
]
255 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
259 so
= 1 if spr
['XER'][XER_bits
['SO']] else 0
260 ov
= 1 if spr
['XER'][XER_bits
['OV']] else 0
261 ov32
= 1 if spr
['XER'][XER_bits
['OV32']] else 0
262 print("before: so/ov/32", so
, ov
, ov32
)
264 # ask the decoder to decode this binary data (endian'd)
266 yield pdecode2
.dec
.bigendian
.eq(bigendian
)
267 yield instruction
.eq(ins
) # raw binary instr.
269 fn_unit
= yield pdecode2
.e
.do
.fn_unit
270 self
.assertEqual(fn_unit
, Function
.DIV
.value
)
271 yield from set_alu_inputs(alu
, pdecode2
, isa_sim
)
273 # set valid for one cycle, propagate through pipeline..
274 # note that it is critically important to do this
275 # for DIV otherwise it starts trying to produce
277 yield alu
.p
.valid_i
.eq(1)
279 yield alu
.p
.valid_i
.eq(0)
281 opname
= code
.split(' ')[0]
282 yield from isa_sim
.call(opname
)
283 index
= isa_sim
.pc
.CIA
.value
//4
285 vld
= yield alu
.n
.valid_o
289 vld
= yield alu
.n
.valid_o
290 # bug #425 investigation
291 do
= alu
.pipe_end
.div_out
293 is_32bit
= yield ctx_op
.is_32bit
294 is_signed
= yield ctx_op
.is_signed
295 quotient_root
= yield do
.i
.core
.quotient_root
296 quotient_65
= yield do
.quotient_65
297 dive_abs_ov32
= yield do
.i
.dive_abs_ov32
298 div_by_zero
= yield do
.i
.div_by_zero
299 quotient_neg
= yield do
.quotient_neg
300 print("32bit", hex(is_32bit
))
301 print("signed", hex(is_signed
))
302 print("quotient_root", hex(quotient_root
))
303 print("quotient_65", hex(quotient_65
))
304 print("div_by_zero", hex(div_by_zero
))
305 print("dive_abs_ov32", hex(dive_abs_ov32
))
306 print("quotient_neg", hex(quotient_neg
))
311 # XXX sim._state is an internal variable
312 # and timeline does not exist
313 # AttributeError: '_SimulatorState' object
314 # has no attribute 'timeline'
315 # TODO: raise bugreport with whitequark
316 # requesting a public API to access this "officially"
317 # XXX print("time:", sim._state.timeline.now)
318 yield from self
.check_alu_outputs(alu
, pdecode2
,
321 sim
.add_sync_process(process
)
322 with sim
.write_vcd(f
"div_simulator_{div_pipe_kind.name}.vcd",
323 f
"div_simulator_{div_pipe_kind.name}.gtkw",
327 def check_alu_outputs(self
, alu
, dec2
, sim
, code
):
329 rc
= yield dec2
.e
.do
.rc
.data
330 cridx_ok
= yield dec2
.e
.write_cr
.ok
331 cridx
= yield dec2
.e
.write_cr
.data
333 print("check extra output", repr(code
), cridx_ok
, cridx
)
335 self
.assertEqual(cridx
, 0, code
)
340 yield from ALUHelpers
.get_cr_a(res
, alu
, dec2
)
341 yield from ALUHelpers
.get_xer_ov(res
, alu
, dec2
)
342 yield from ALUHelpers
.get_int_o(res
, alu
, dec2
)
343 yield from ALUHelpers
.get_xer_so(res
, alu
, dec2
)
345 print("res output", res
)
347 yield from ALUHelpers
.get_sim_int_o(sim_o
, sim
, dec2
)
348 yield from ALUHelpers
.get_wr_sim_cr_a(sim_o
, sim
, dec2
)
349 yield from ALUHelpers
.get_sim_xer_ov(sim_o
, sim
, dec2
)
350 yield from ALUHelpers
.get_sim_xer_so(sim_o
, sim
, dec2
)
352 print("sim output", sim_o
)
354 ALUHelpers
.check_int_o(self
, res
, sim_o
, code
)
355 ALUHelpers
.check_cr_a(self
, res
, sim_o
, "CR%d %s" % (cridx
, code
))
356 ALUHelpers
.check_xer_ov(self
, res
, sim_o
, code
)
357 ALUHelpers
.check_xer_so(self
, res
, sim_o
, code
)
359 oe
= yield dec2
.e
.do
.oe
.oe
360 oe_ok
= yield dec2
.e
.do
.oe
.ok
361 print("oe, oe_ok", oe
, oe_ok
)
362 if not oe
or not oe_ok
:
363 # if OE not enabled, XER SO and OV must not be activated
364 so_ok
= yield alu
.n
.data_o
.xer_so
.ok
365 ov_ok
= yield alu
.n
.data_o
.xer_ov
.ok
366 print("so, ov", so_ok
, ov_ok
)
367 self
.assertEqual(ov_ok
, False, code
)
368 self
.assertEqual(so_ok
, False, code
)
370 def test_run_div_pipe_core(self
):
371 self
.run_all(DivPipeKind
.DivPipeCore
)
373 def test_run_fsm_div_core(self
):
374 self
.run_all(DivPipeKind
.FSMDivCore
)
376 def test_run_sim_only(self
):
377 self
.run_all(DivPipeKind
.SimOnly
)
380 if __name__
== "__main__":