src/soc/fu/div/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import (TestCase, ALUHelpers)
  16 from soc.fu.div.pipeline import DIVBasePipe
  17 from soc.fu.div.pipe_data import DIVPipeSpec
  18 import random
  19
  20
  21 def get_cu_inputs(dec2, sim):
  22     """naming (res) must conform to DIVFunctionUnit input regspec
  23     """
  24     res = {}
  25
  26     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
  27     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
  28     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
  29
  30     print ("alu get_cu_inputs", res)
  31
  32     return res
  33
  34
  35
  36 def set_alu_inputs(alu, dec2, sim):
  37     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  38     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  39     # and place it into data_i.b
  40
  41     inp = yield from get_cu_inputs(dec2, sim)
  42     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  43     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  44
  45     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  46
  47
  48 # This test bench is a bit different than is usual. Initially when I
  49 # was writing it, I had all of the tests call a function to create a
  50 # device under test and simulator, initialize the dut, run the
  51 # simulation for ~2 cycles, and assert that the dut output what it
  52 # should have. However, this was really slow, since it needed to
  53 # create and tear down the dut and simulator for every test case.
  54
  55 # Now, instead of doing that, every test case in DIVTestCase puts some
  56 # data into the test_data list below, describing the instructions to
  57 # be tested and the initial state. Once all the tests have been run,
  58 # test_data gets passed to TestRunner which then sets up the DUT and
  59 # simulator once, runs all the data through it, and asserts that the
  60 # results match the pseudocode sim at every cycle.
  61
  62 # By doing this, I've reduced the time it takes to run the test suite
  63 # massively. Before, it took around 1 minute on my computer, now it
  64 # takes around 3 seconds
  65
  66
  67 class DIVTestCase(FHDLTestCase):
  68     test_data = []
  69
  70     def __init__(self, name):
  71         super().__init__(name)
  72         self.test_name = name
  73
  74     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  75         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  76         self.test_data.append(tc)
  77
  78     def test_0_regression(self):
  79         for i in range(40):
  80             lst = ["divwo 3, 1, 2"]
  81             initial_regs = [0] * 32
  82             initial_regs[1] = 0xbc716835f32ac00c
  83             initial_regs[2] = 0xcdf69a7f7042db66
  84             self.run_tst_program(Program(lst), initial_regs)
  85
  86     def test_1_regression(self):
  87         lst = ["divwo 3, 1, 2"]
  88         initial_regs = [0] * 32
  89         initial_regs[1] = 0x10000000000000000-4
  90         initial_regs[2] = 0x10000000000000000-2
  91         self.run_tst_program(Program(lst), initial_regs)
  92
  93     def test_2_regression(self):
  94         lst = ["divwo 3, 1, 2"]
  95         initial_regs = [0] * 32
  96         initial_regs[1] = 0xffffffffffff9321
  97         initial_regs[2] = 0xffffffffffff7012
  98         self.run_tst_program(Program(lst), initial_regs)
  99
 100     def test_3_regression(self):
 101         lst = ["divwo. 3, 1, 2"]
 102         initial_regs = [0] * 32
 103         initial_regs[1] = 0x1b8e32f2458746af
 104         initial_regs[2] = 0x6b8aee2ccf7d62e9
 105         self.run_tst_program(Program(lst), initial_regs)
 106
 107     def test_4_regression(self):
 108         lst = ["divw 3, 1, 2"]
 109         initial_regs = [0] * 32
 110         initial_regs[1] = 0x1c4e6c2f3aa4a05c
 111         initial_regs[2] = 0xe730c2eed6cc8dd7
 112         self.run_tst_program(Program(lst), initial_regs)
 113
 114     def test_5_regression(self):
 115         lst = ["divw 3, 1, 2",
 116                "divwo. 6, 4, 5"]
 117         initial_regs = [0] * 32
 118         initial_regs[1] = 0x1c4e6c2f3aa4a05c
 119         initial_regs[2] = 0xe730c2eed6cc8dd7
 120         initial_regs[4] = 0x1b8e32f2458746af
 121         initial_regs[5] = 0x6b8aee2ccf7d62e9
 122         self.run_tst_program(Program(lst), initial_regs)
 123
 124     def test_rand_divw(self):
 125         insns = ["divw", "divw.", "divwo", "divwo."]
 126         for i in range(40):
 127             choice = random.choice(insns)
 128             lst = [f"{choice} 3, 1, 2"]
 129             initial_regs = [0] * 32
 130             initial_regs[1] = random.randint(0, (1<<64)-1)
 131             initial_regs[2] = random.randint(0, (1<<64)-1)
 132             self.run_tst_program(Program(lst), initial_regs)
 133
 134     def test_ilang(self):
 135         pspec = DIVPipeSpec(id_wid=2)
 136         alu = DIVBasePipe(pspec)
 137         vl = rtlil.convert(alu, ports=alu.ports())
 138         with open("div_pipeline.il", "w") as f:
 139             f.write(vl)
 140
 141
 142 class TestRunner(FHDLTestCase):
 143     def __init__(self, test_data):
 144         super().__init__("run_all")
 145         self.test_data = test_data
 146
 147     def run_all(self):
 148         m = Module()
 149         comb = m.d.comb
 150         instruction = Signal(32)
 151
 152         pdecode = create_pdecode()
 153
 154         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 155
 156         pspec = DIVPipeSpec(id_wid=2)
 157         m.submodules.alu = alu = DIVBasePipe(pspec)
 158
 159         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 160         comb += alu.n.ready_i.eq(1)
 161         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 162         sim = Simulator(m)
 163
 164         sim.add_clock(1e-6)
 165         def process():
 166             for test in self.test_data:
 167                 print(test.name)
 168                 program = test.program
 169                 self.subTest(test.name)
 170                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
 171                                 test.mem, test.msr)
 172                 gen = program.generate_instructions()
 173                 instructions = list(zip(gen, program.assembly.splitlines()))
 174                 yield Settle()
 175
 176                 index = sim.pc.CIA.value//4
 177                 while index < len(instructions):
 178                     ins, code = instructions[index]
 179
 180                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 181                     print(code)
 182                     if 'XER' in sim.spr:
 183                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 184                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 185                         ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 186                         print ("before: so/ov/32", so, ov, ov32)
 187
 188                     # ask the decoder to decode this binary data (endian'd)
 189                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 190                     yield instruction.eq(ins)          # raw binary instr.
 191                     yield Settle()
 192                     fn_unit = yield pdecode2.e.do.fn_unit
 193                     self.assertEqual(fn_unit, Function.DIV.value)
 194                     yield from set_alu_inputs(alu, pdecode2, sim)
 195
 196                     # set valid for one cycle, propagate through pipeline...
 197                     yield alu.p.valid_i.eq(1)
 198                     yield
 199                     yield alu.p.valid_i.eq(0)
 200
 201                     opname = code.split(' ')[0]
 202                     yield from sim.call(opname)
 203                     index = sim.pc.CIA.value//4
 204
 205                     vld = yield alu.n.valid_o
 206                     while not vld:
 207                         yield
 208                         vld = yield alu.n.valid_o
 209                     yield
 210
 211                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 212                     yield Settle()
 213
 214         sim.add_sync_process(process)
 215         with sim.write_vcd("div_simulator.vcd", "div_simulator.gtkw",
 216                             traces=[]):
 217             sim.run()
 218
 219     def check_alu_outputs(self, alu, dec2, sim, code):
 220
 221         rc = yield dec2.e.do.rc.data
 222         cridx_ok = yield dec2.e.write_cr.ok
 223         cridx = yield dec2.e.write_cr.data
 224
 225         print ("check extra output", repr(code), cridx_ok, cridx)
 226         if rc:
 227             self.assertEqual(cridx, 0, code)
 228
 229         sim_o = {}
 230         res = {}
 231
 232         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 233         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
 234         yield from ALUHelpers.get_int_o(res, alu, dec2)
 235         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 236
 237         print ("res output", res)
 238
 239         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 240         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 241         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
 242         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 243
 244         print ("sim output", sim_o)
 245
 246         ALUHelpers.check_int_o(self, res, sim_o, code)
 247         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 248         ALUHelpers.check_xer_ov(self, res, sim_o, code)
 249         ALUHelpers.check_xer_so(self, res, sim_o, code)
 250
 251         oe = yield dec2.e.do.oe.oe
 252         oe_ok = yield dec2.e.do.oe.ok
 253         print ("oe, oe_ok", oe, oe_ok)
 254         if not oe or not oe_ok:
 255             # if OE not enabled, XER SO and OV must not be activated
 256             so_ok = yield alu.n.data_o.xer_so.ok
 257             ov_ok = yield alu.n.data_o.xer_ov.ok
 258             print ("so, ov", so_ok, ov_ok)
 259             self.assertEqual(ov_ok, False, code)
 260             self.assertEqual(so_ok, False, code)
 261
 262
 263 if __name__ == "__main__":
 264     unittest.main(exit=False)
 265     suite = unittest.TestSuite()
 266     suite.addTest(TestRunner(DIVTestCase.test_data))
 267
 268     runner = unittest.TextTestRunner()
 269     runner.run(suite)