2 from nmigen
.cli
import rtlil
3 from soc
.fu
.div
.pipe_data
import DivPipeSpec
, DivPipeKind
4 from soc
.fu
.div
.pipeline
import DivBasePipe
7 class TestPipeIlang(unittest
.TestCase
):
8 def write_ilang(self
, div_pipe_kind
):
9 pspec
= DivPipeSpec(id_wid
=2, div_pipe_kind
=div_pipe_kind
)
10 alu
= DivBasePipe(pspec
)
11 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
12 with
open(f
"div_pipeline_{div_pipe_kind.name}.il", "w") as f
:
15 def test_div_pipe_core(self
):
16 self
.write_ilang(DivPipeKind
.DivPipeCore
)
18 def test_fsm_div_core(self
):
19 self
.write_ilang(DivPipeKind
.FSMDivCore
)
21 def test_sim_only(self
):
22 self
.write_ilang(DivPipeKind
.SimOnly
)
25 if __name__
== "__main__":