add link to regspecs on wiki
[soc.git] / src / soc / fu / ldst / ldst_input_record.py
1 from nmigen.hdl.rec import Record, Layout
2
3 from soc.decoder.power_enums import InternalOp, Function
4
5
6 class CompLDSTOpSubset(Record):
7 """CompLDSTOpSubset
8
9 a copy of the relevant subset information from Decode2Execute1Type
10 needed for LD/ST operations. use with eq_from_execute1 (below) to
11 grab subsets.
12 """
13 def __init__(self, name=None):
14 layout = (('insn_type', InternalOp),
15 ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
16 ('is_32bit', 1),
17 ('is_signed', 1),
18 ('data_len', 4),
19 ('byte_reverse', 1),
20 ('sign_extend', 1),
21 ('update', 1))
22
23 Record.__init__(self, Layout(layout), name=name)
24
25 # grrr. Record does not have kwargs
26 self.insn_type.reset_less = True
27 self.is_32bit.reset_less = True
28 self.is_signed.reset_less = True
29 self.data_len.reset_less = True
30 self.byte_reverse.reset_less = True
31 self.sign_extend.reset_less = True
32 self.update.reset_less = True
33
34 def eq_from_execute1(self, other):
35 """ use this to copy in from Decode2Execute1Type
36 """
37 res = []
38 for fname, sig in self.fields.items():
39 eqfrom = other.fields[fname]
40 res.append(sig.eq(eqfrom))
41 return res
42
43 def ports(self):
44 return [self.insn_type,
45 self.is_32bit,
46 self.is_signed,
47 self.data_len,
48 self.byte_reverse,
49 self.sign_extend,
50 self.update,
51 ]
52