src/soc/fu/ldst/loadstore.py

   1 """LoadStore1 FSM.
   2
   3 based on microwatt loadstore1.vhdl, but conforming to PortInterface.
   4 unlike loadstore1.vhdl this does *not* deal with actual Load/Store
   5 ops: that job is handled by LDSTCompUnit, which talks to LoadStore1
   6 by way of PortInterface.  PortInterface is where things need extending,
   7 such as adding dcbz support, etc.
   8
   9 this module basically handles "pure" load / store operations, and
  10 its first job is to ask the D-Cache for the data.  if that fails,
  11 the second task (if virtual memory is enabled) is to ask the MMU
  12 to perform a TLB, then to go *back* to the cache and ask again.
  13
  14 Links:
  15
  16 * https://bugs.libre-soc.org/show_bug.cgi?id=465
  17
  18 """
  19
  20 from nmigen import (Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux,
  21                     Record, Memory,
  22                     Const)
  23 from nmutil.iocontrol import RecordObject
  24 from nmutil.util import rising_edge, Display
  25 from enum import Enum, unique
  26
  27 from soc.experiment.dcache import DCache
  28 from soc.experiment.icache import ICache
  29 from soc.experiment.pimem import PortInterfaceBase
  30 from soc.experiment.mem_types import LoadStore1ToMMUType
  31 from soc.experiment.mem_types import MMUToLoadStore1Type
  32
  33 from soc.minerva.wishbone import make_wb_layout
  34 from soc.bus.sram import SRAM
  35 from nmutil.util import Display
  36
  37
  38 @unique
  39 class State(Enum):
  40     IDLE = 0       # ready for instruction
  41     ACK_WAIT = 1   # waiting for ack from dcache
  42     MMU_LOOKUP = 2 # waiting for MMU to look up translation
  43     #SECOND_REQ = 3 # second request for unaligned transfer
  44
  45 @unique
  46 class Misalign(Enum):
  47     ONEWORD = 0    # only one word needed, all good
  48     NEED2WORDS = 1 # need to send/receive two words
  49     WAITFIRST = 2  # waiting for the first word
  50     WAITSECOND = 3 # waiting for the second word
  51
  52
  53 # captures the LDSTRequest from the PortInterface, which "blips" most
  54 # of this at us (pipeline-style).
  55 class LDSTRequest(RecordObject):
  56     def __init__(self, name=None):
  57         RecordObject.__init__(self, name=name)
  58
  59         self.load          = Signal()
  60         self.dcbz          = Signal()
  61         self.raddr          = Signal(64)
  62         # self.store_data    = Signal(64) # this is already sync (on a delay)
  63         self.byte_sel      = Signal(16)
  64         self.nc            = Signal()              # non-cacheable access
  65         self.virt_mode     = Signal()
  66         self.priv_mode     = Signal()
  67         self.mode_32bit    = Signal() # XXX UNUSED AT PRESENT
  68         self.alignstate    = Signal(Misalign) # progress of alignment request
  69         self.align_intr    = Signal()
  70         # atomic (LR/SC reservation)
  71         self.reserve       = Signal()
  72         self.atomic        = Signal()
  73         self.atomic_last   = Signal()
  74
  75
  76 # glue logic for microwatt mmu and dcache
  77 class LoadStore1(PortInterfaceBase):
  78     def __init__(self, pspec):
  79         self.pspec = pspec
  80         self.disable_cache = (hasattr(pspec, "disable_cache") and
  81                               pspec.disable_cache == True)
  82         regwid = pspec.reg_wid
  83         addrwid = pspec.addr_wid
  84
  85         super().__init__(regwid, addrwid)
  86         self.dcache = DCache(pspec)
  87         self.icache = ICache(pspec)
  88         # these names are from the perspective of here (LoadStore1)
  89         self.d_out  = self.dcache.d_in     # in to dcache is out for LoadStore
  90         self.d_in = self.dcache.d_out      # out from dcache is in for LoadStore
  91         self.i_out  = self.icache.i_in     # in to icache is out for LoadStore
  92         self.i_in = self.icache.i_out      # out from icache is in for LoadStore
  93         self.m_out  = LoadStore1ToMMUType("m_out") # out *to* MMU
  94         self.m_in = MMUToLoadStore1Type("m_in")   # in *from* MMU
  95         self.req = LDSTRequest(name="ldst_req")
  96
  97         # TODO, convert dcache wb_in/wb_out to "standard" nmigen Wishbone bus
  98         self.dbus = Record(make_wb_layout(pspec))
  99         self.ibus = Record(make_wb_layout(pspec))
 100
 101         # for creating a single clock blip to DCache
 102         self.d_valid = Signal()
 103         self.d_w_valid = Signal()
 104         self.d_validblip = Signal()
 105
 106         # state info for LD/ST
 107         self.done          = Signal()
 108         self.done_delay    = Signal()
 109         # latch most of the input request
 110         self.load          = Signal()
 111         self.tlbie         = Signal()
 112         self.dcbz          = Signal()
 113         self.raddr          = Signal(64)
 114         self.maddr          = Signal(64)
 115         self.store_data    = Signal(128)   # 128-bit to cope with
 116         self.load_data     = Signal(128)   # misalignment
 117         self.load_data_delay = Signal(128) # perform 2 LD/STs
 118         self.byte_sel      = Signal(16)    # also for misaligned, 16-bit
 119         self.alignstate    = Signal(Misalign) # progress of alignment request
 120         #self.xerc         : xer_common_t;
 121         #self.rc            = Signal()
 122         self.nc            = Signal()              # non-cacheable access
 123         self.mode_32bit    = Signal() # XXX UNUSED AT PRESENT
 124         self.state         = Signal(State)
 125         self.instr_fault   = Signal()  # indicator to request i-cache MMU lookup
 126         self.r_instr_fault  = Signal() # accessed in external_busy
 127         self.priv_mode     = Signal() # only for instruction fetch (not LDST)
 128         self.align_intr    = Signal()
 129         self.busy          = Signal()
 130         self.wait_dcache   = Signal()
 131         self.wait_mmu      = Signal()
 132         self.lrsc_misalign = Signal()
 133         #self.intr_vec     : integer range 0 to 16#fff#;
 134         #self.nia           = Signal(64)
 135         #self.srr1          = Signal(16)
 136         # use these to set the dsisr or dar respectively
 137         self.mmu_set_spr    = Signal()
 138         self.mmu_set_dsisr  = Signal()
 139         self.mmu_set_dar    = Signal()
 140         self.sprval_in      = Signal(64)
 141
 142         # ONLY access these read-only, do NOT attempt to change
 143         self.dsisr          = Signal(32)
 144         self.dar            = Signal(64)
 145
 146     # when external_busy set, do not allow PortInterface to proceed
 147     def external_busy(self, m):
 148         return self.instr_fault | self.r_instr_fault
 149
 150     def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz):
 151         m.d.comb += self.req.load.eq(0) # store operation
 152         m.d.comb += self.req.byte_sel.eq(mask)
 153         m.d.comb += self.req.raddr.eq(addr)
 154         m.d.comb += self.req.priv_mode.eq(~msr.pr) # not-problem  ==> priv
 155         m.d.comb += self.req.virt_mode.eq(msr.dr) # DR ==> virt
 156         m.d.comb += self.req.mode_32bit.eq(~msr.sf) # not-sixty-four ==> 32bit
 157         m.d.comb += self.req.dcbz.eq(is_dcbz)
 158         with m.If(misalign):
 159             m.d.comb += self.req.alignstate.eq(Misalign.NEED2WORDS)
 160
 161         # m.d.comb += Display("set_wr_addr %i dcbz %i",addr,is_dcbz)
 162
 163         # option to disable the cache entirely for write
 164         if self.disable_cache:
 165             m.d.comb += self.req.nc.eq(1)
 166
 167         # dcbz cannot do no-cache
 168         with m.If(is_dcbz & self.req.nc):
 169             m.d.comb += self.req.align_intr.eq(1)
 170
 171         # hmm, rather than add yet another argument to set_wr_addr
 172         # read direct from PortInterface
 173         m.d.comb += self.req.reserve.eq(self.pi.reserve) # atomic request
 174         m.d.comb += self.req.atomic.eq(~self.lrsc_misalign)
 175         m.d.comb += self.req.atomic_last.eq(~self.lrsc_misalign)
 176
 177         return None
 178
 179     def set_rd_addr(self, m, addr, mask, misalign, msr):
 180         m.d.comb += self.d_valid.eq(1)
 181         m.d.comb += self.req.load.eq(1) # load operation
 182         m.d.comb += self.req.byte_sel.eq(mask)
 183         m.d.comb += self.req.raddr.eq(addr)
 184         m.d.comb += self.req.priv_mode.eq(~msr.pr) # not-problem  ==> priv
 185         m.d.comb += self.req.virt_mode.eq(msr.dr) # DR ==> virt
 186         m.d.comb += self.req.mode_32bit.eq(~msr.sf) # not-sixty-four ==> 32bit
 187         # BAD HACK! disable cacheing on LD when address is 0xCxxx_xxxx
 188         # this is for peripherals. same thing done in Microwatt loadstore1.vhdl
 189         with m.If(addr[28:] == Const(0xc, 4)):
 190             m.d.comb += self.req.nc.eq(1)
 191         # option to disable the cache entirely for read
 192         if self.disable_cache:
 193             m.d.comb += self.req.nc.eq(1)
 194         with m.If(misalign):
 195             m.d.comb += self.req.alignstate.eq(Misalign.NEED2WORDS)
 196
 197         # hmm, rather than add yet another argument to set_rd_addr
 198         # read direct from PortInterface
 199         m.d.comb += self.req.reserve.eq(self.pi.reserve) # atomic request
 200         m.d.comb += self.req.atomic.eq(~self.lrsc_misalign)
 201         m.d.comb += self.req.atomic_last.eq(~self.lrsc_misalign)
 202
 203         return None #FIXME return value
 204
 205     def set_wr_data(self, m, data, wen):
 206         # do the "blip" on write data
 207         m.d.comb += self.d_valid.eq(1)
 208         # put data into comb which is picked up in main elaborate()
 209         m.d.comb += self.d_w_valid.eq(1)
 210         m.d.comb += self.store_data.eq(data)
 211         m.d.comb += self.pi.store_done.eq(self.d_in.store_done)
 212         st_ok = self.done # TODO indicates write data is valid
 213         return st_ok
 214
 215     def get_rd_data(self, m):
 216         ld_ok = self.done_delay # indicates read data is valid
 217         data = self.load_data_delay   # actual read data
 218         return data, ld_ok
 219
 220     def elaborate(self, platform):
 221         m = super().elaborate(platform)
 222         comb, sync = m.d.comb, m.d.sync
 223
 224         # microwatt takes one more cycle before next operation can be issued
 225         sync += self.done_delay.eq(self.done)
 226         #sync += self.load_data_delay[0:64].eq(self.load_data[0:64])
 227
 228         # create dcache and icache module
 229         m.submodules.dcache = dcache = self.dcache
 230         m.submodules.icache = icache = self.icache
 231
 232         # temp vars
 233         d_out, d_in, dbus = self.d_out, self.d_in, self.dbus
 234         i_out, i_in, ibus = self.i_out, self.i_in, self.ibus
 235         m_out, m_in = self.m_out, self.m_in
 236         exc = self.pi.exc_o
 237         exception = exc.happened
 238         mmureq = Signal()
 239
 240         # copy of address, but gets over-ridden for instr_fault
 241         maddr = Signal(64)
 242         m.d.comb += maddr.eq(self.raddr)
 243
 244         # check for LR/SC misalignment, used in set_rd/wr_addr above
 245         comb += self.lrsc_misalign.eq(((self.pi.data_len[0:3]-1) &
 246                                         self.req.raddr[0:3]).bool())
 247
 248         # create a blip (single pulse) on valid read/write request
 249         # this can be over-ridden in the FSM to get dcache to re-run
 250         # a request when MMU_LOOKUP completes.
 251         m.d.comb += self.d_validblip.eq(rising_edge(m, self.d_valid))
 252         ldst_r = LDSTRequest("ldst_r")
 253         sync += Display("MMUTEST: LoadStore1 d_in.error=%i",d_in.error)
 254
 255         # fsm skeleton
 256         with m.Switch(self.state):
 257             with m.Case(State.IDLE):
 258                 with m.If((self.d_validblip | self.instr_fault) &
 259                           ~exc.happened):
 260                     comb += self.busy.eq(1)
 261                     sync += self.state.eq(State.ACK_WAIT)
 262                     sync += ldst_r.eq(self.req) # copy of LDSTRequest on "blip"
 263                     # sync += Display("validblip self.req.virt_mode=%i",
 264                     #                 self.req.virt_mode)
 265                     with m.If(self.instr_fault):
 266                         comb += mmureq.eq(1)
 267                         sync += self.r_instr_fault.eq(1)
 268                         comb += maddr.eq(self.maddr)
 269                         sync += self.state.eq(State.MMU_LOOKUP)
 270                     with m.Else():
 271                         sync += self.r_instr_fault.eq(0)
 272                     # if the LD/ST requires two dwords, move to waiting
 273                     # for first word
 274                     with m.If(self.req.alignstate == Misalign.NEED2WORDS):
 275                         sync += ldst_r.alignstate.eq(Misalign.WAITFIRST)
 276                 with m.Else():
 277                     sync += ldst_r.eq(0)
 278
 279             # waiting for completion
 280             with m.Case(State.ACK_WAIT):
 281                 sync += Display("MMUTEST: ACK_WAIT")
 282                 comb += self.busy.eq(~exc.happened)
 283
 284                 with m.If(d_in.error):
 285                     # cache error is not necessarily "final", it could
 286                     # be that it was just a TLB miss
 287                     with m.If(d_in.cache_paradox):
 288                         comb += exception.eq(1)
 289                         sync += self.state.eq(State.IDLE)
 290                         sync += ldst_r.eq(0)
 291                         sync += Display("cache error -> update dsisr")
 292                         sync += self.dsisr[63 - 38].eq(~ldst_r.load)
 293                         # XXX there is no architected bit for this
 294                         # (probably should be a machine check in fact)
 295                         sync += self.dsisr[63 - 35].eq(d_in.cache_paradox)
 296                         sync += self.r_instr_fault.eq(0)
 297
 298                     with m.Else():
 299                         # Look up the translation for TLB miss
 300                         # and also for permission error and RC error
 301                         # in case the PTE has been updated.
 302                         comb += mmureq.eq(1)
 303                         sync += self.state.eq(State.MMU_LOOKUP)
 304                 with m.If(d_in.valid):
 305                     with m.If(self.done):
 306                         sync += Display("ACK_WAIT, done %x", self.raddr)
 307                     with m.If(ldst_r.alignstate == Misalign.ONEWORD):
 308                         # done if there is only one dcache operation
 309                         sync += self.state.eq(State.IDLE)
 310                         sync += ldst_r.eq(0)
 311                         with m.If(ldst_r.load):
 312                             m.d.comb += self.load_data.eq(d_in.data)
 313                             sync += self.load_data_delay[0:64].eq(d_in.data)
 314                         m.d.comb += self.done.eq(~mmureq) # done if not MMU
 315                     with m.Elif(ldst_r.alignstate == Misalign.WAITFIRST):
 316                         # first LD done: load data, initiate 2nd request.
 317                         # leave in ACK_WAIT state
 318                         with m.If(ldst_r.load):
 319                             m.d.comb += self.load_data[0:63].eq(d_in.data)
 320                             sync += self.load_data_delay[0:64].eq(d_in.data)
 321                         # mmm kinda cheating, make a 2nd blip
 322                         m.d.comb += self.d_validblip.eq(1)
 323                         comb += self.req.eq(ldst_r) # from copy of request
 324                         comb += self.req.raddr.eq(ldst_r.raddr + 8)
 325                         comb += self.req.byte_sel.eq(ldst_r.byte_sel[8:])
 326                         comb += self.req.alignstate.eq(Misalign.WAITSECOND)
 327                         sync += ldst_r.raddr.eq(ldst_r.raddr + 8)
 328                         sync += ldst_r.byte_sel.eq(ldst_r.byte_sel[8:])
 329                         sync += ldst_r.alignstate.eq(Misalign.WAITSECOND)
 330                         sync += Display("    second req %x", self.req.raddr)
 331                     with m.Elif(ldst_r.alignstate == Misalign.WAITSECOND):
 332                         sync += Display("    done second %x", d_in.data)
 333                         # done second load
 334                         sync += self.state.eq(State.IDLE)
 335                         sync += ldst_r.eq(0)
 336                         with m.If(ldst_r.load):
 337                             m.d.comb += self.load_data[64:128].eq(d_in.data)
 338                             sync += self.load_data_delay[64:128].eq(d_in.data)
 339                         m.d.comb += self.done.eq(~mmureq) # done if not MMU
 340
 341             # waiting here for the MMU TLB lookup to complete.
 342             # either re-try the dcache lookup or throw MMU exception
 343             with m.Case(State.MMU_LOOKUP):
 344                 comb += self.busy.eq(~exception)
 345                 with m.If(m_in.done):
 346                     with m.If(~self.r_instr_fault):
 347                         sync += Display("MMU_LOOKUP, done %x -> %x",
 348                                         self.raddr, d_out.addr)
 349                         # retry the request now that the MMU has
 350                         # installed a TLB entry, if not exception raised
 351                         m.d.comb += self.d_out.valid.eq(~exception)
 352                         sync += self.state.eq(State.ACK_WAIT)
 353                     with m.Else():
 354                         sync += self.state.eq(State.IDLE)
 355                         sync += self.r_instr_fault.eq(0)
 356                         comb += self.done.eq(1)
 357
 358                 with m.If(m_in.err):
 359                     # MMU RADIX exception thrown. XXX
 360                     # TODO: critical that the write here has to
 361                     # notify the MMU FSM of the change to dsisr
 362                     comb += exception.eq(1)
 363                     comb += self.done.eq(1)
 364                     sync += Display("MMU RADIX exception thrown")
 365                     sync += self.dsisr[63 - 33].eq(m_in.invalid)
 366                     sync += self.dsisr[63 - 36].eq(m_in.perm_error) # noexec
 367                     sync += self.dsisr[63 - 38].eq(~ldst_r.load)
 368                     sync += self.dsisr[63 - 44].eq(m_in.badtree)
 369                     sync += self.dsisr[63 - 45].eq(m_in.rc_error)
 370                     sync += self.state.eq(State.IDLE)
 371                     # exception thrown, clear out instruction fault state
 372                     sync += self.r_instr_fault.eq(0)
 373
 374         # MMU FSM communicating a request to update DSISR or DAR (OP_MTSPR)
 375         with m.If(self.mmu_set_spr):
 376             with m.If(self.mmu_set_dsisr):
 377                 sync += self.dsisr.eq(self.sprval_in)
 378             with m.If(self.mmu_set_dar):
 379                 sync += self.dar.eq(self.sprval_in)
 380
 381         # hmmm, alignment occurs in set_rd_addr/set_wr_addr, note exception
 382         with m.If(self.align_intr):
 383             comb += exc.happened.eq(1)
 384         # check for updating DAR
 385         with m.If(exception):
 386             sync += Display("exception %x", self.raddr)
 387             # alignment error: store address in DAR
 388             with m.If(self.align_intr):
 389                 sync += Display("alignment error: addr in DAR %x", self.raddr)
 390                 sync += self.dar.eq(self.raddr)
 391             with m.Elif(~self.r_instr_fault):
 392                 sync += Display("not instr fault, addr in DAR %x", self.raddr)
 393                 sync += self.dar.eq(self.raddr)
 394
 395         # when done or exception, return to idle state
 396         with m.If(self.done | exception):
 397             sync += self.state.eq(State.IDLE)
 398             comb += self.busy.eq(0)
 399
 400         # happened, alignment, instr_fault, invalid.
 401         # note that all of these flow through - eventually to the TRAP
 402         # pipeline, via PowerDecoder2.
 403         comb += self.align_intr.eq(self.req.align_intr)
 404         comb += exc.invalid.eq(m_in.invalid)
 405         comb += exc.alignment.eq(self.align_intr)
 406         comb += exc.instr_fault.eq(self.r_instr_fault)
 407         # badtree, perm_error, rc_error, segment_fault
 408         comb += exc.badtree.eq(m_in.badtree)
 409         comb += exc.perm_error.eq(m_in.perm_error)
 410         comb += exc.rc_error.eq(m_in.rc_error)
 411         comb += exc.segment_fault.eq(m_in.segerr)
 412
 413         # TODO, connect dcache wb_in/wb_out to "standard" nmigen Wishbone bus
 414         comb += dbus.adr.eq(dcache.bus.adr)
 415         comb += dbus.dat_w.eq(dcache.bus.dat_w)
 416         comb += dbus.sel.eq(dcache.bus.sel)
 417         comb += dbus.cyc.eq(dcache.bus.cyc)
 418         comb += dbus.stb.eq(dcache.bus.stb)
 419         comb += dbus.we.eq(dcache.bus.we)
 420
 421         comb += dcache.bus.dat_r.eq(dbus.dat_r)
 422         comb += dcache.bus.ack.eq(dbus.ack)
 423         if hasattr(dbus, "stall"):
 424             comb += dcache.bus.stall.eq(dbus.stall)
 425
 426         # update out d data when flag set
 427         with m.If(self.d_w_valid):
 428             with m.If(ldst_r.alignstate == Misalign.WAITSECOND):
 429                 m.d.sync += d_out.data.eq(self.store_data[64:128])
 430             with m.Else():
 431                 m.d.sync += d_out.data.eq(self.store_data[0:64])
 432         #with m.Else():
 433         #    m.d.sync += d_out.data.eq(0)
 434         # unit test passes with that change
 435
 436         # this must move into the FSM, conditionally noticing that
 437         # the "blip" comes from self.d_validblip.
 438         # task 1: look up in dcache
 439         # task 2: if dcache fails, look up in MMU.
 440         # do **NOT** confuse the two.
 441         with m.If(self.d_validblip):
 442             m.d.comb += self.d_out.valid.eq(~exc.happened)
 443             m.d.comb += d_out.load.eq(self.req.load)
 444             m.d.comb += d_out.byte_sel.eq(self.req.byte_sel)
 445             m.d.comb += self.raddr.eq(self.req.raddr)
 446             m.d.comb += d_out.nc.eq(self.req.nc)
 447             m.d.comb += d_out.priv_mode.eq(self.req.priv_mode)
 448             m.d.comb += d_out.virt_mode.eq(self.req.virt_mode)
 449             m.d.comb += d_out.reserve.eq(self.req.reserve)
 450             m.d.comb += d_out.atomic.eq(self.req.atomic)
 451             m.d.comb += d_out.atomic_last.eq(self.req.atomic_last)
 452             #m.d.comb += Display("validblip dcbz=%i addr=%x",
 453             #self.req.dcbz,self.req.addr)
 454             m.d.comb += d_out.dcbz.eq(self.req.dcbz)
 455         with m.Else():
 456             m.d.comb += d_out.load.eq(ldst_r.load)
 457             m.d.comb += d_out.byte_sel.eq(ldst_r.byte_sel)
 458             m.d.comb += self.raddr.eq(ldst_r.raddr)
 459             m.d.comb += d_out.nc.eq(ldst_r.nc)
 460             m.d.comb += d_out.priv_mode.eq(ldst_r.priv_mode)
 461             m.d.comb += d_out.virt_mode.eq(ldst_r.virt_mode)
 462             m.d.comb += d_out.reserve.eq(ldst_r.reserve)
 463             m.d.comb += d_out.atomic.eq(ldst_r.atomic)
 464             m.d.comb += d_out.atomic_last.eq(ldst_r.atomic_last)
 465             #m.d.comb += Display("no_validblip dcbz=%i addr=%x",
 466             #ldst_r.dcbz,ldst_r.addr)
 467             m.d.comb += d_out.dcbz.eq(ldst_r.dcbz)
 468         m.d.comb += d_out.addr.eq(self.raddr)
 469
 470         # Update outputs to MMU
 471         m.d.comb += m_out.valid.eq(mmureq)
 472         m.d.comb += m_out.iside.eq(self.instr_fault)
 473         m.d.comb += m_out.load.eq(ldst_r.load)
 474         with m.If(self.instr_fault):
 475             m.d.comb += m_out.priv.eq(self.priv_mode)
 476         with m.Else():
 477             m.d.comb += m_out.priv.eq(ldst_r.priv_mode)
 478         m.d.comb += m_out.tlbie.eq(self.tlbie)
 479         # m_out.mtspr <= mmu_mtspr; # TODO
 480         # m_out.sprn <= sprn; # TODO
 481         m.d.comb += m_out.addr.eq(maddr)
 482         # m_out.slbia <= l_in.insn(7); # TODO: no idea what this is
 483         # m_out.rs <= l_in.data; # nope, probably not needed, TODO investigate
 484
 485         return m
 486
 487     def ports(self):
 488         yield from super().ports()
 489         # TODO: memory ports
 490
 491
 492 class TestSRAMLoadStore1(LoadStore1):
 493     def __init__(self, pspec):
 494         super().__init__(pspec)
 495         pspec = self.pspec
 496         # small 32-entry Memory
 497         if (hasattr(pspec, "dmem_test_depth") and
 498                 isinstance(pspec.dmem_test_depth, int)):
 499             depth = pspec.dmem_test_depth
 500         else:
 501             depth = 32
 502         print("TestSRAMBareLoadStoreUnit depth", depth)
 503
 504         self.mem = Memory(width=pspec.reg_wid, depth=depth)
 505
 506     def elaborate(self, platform):
 507         m = super().elaborate(platform)
 508         comb = m.d.comb
 509         m.submodules.sram = sram = SRAM(memory=self.mem, granularity=8,
 510                                         features={'cti', 'bte', 'err'})
 511         dbus = self.dbus
 512
 513         # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
 514         # note: SRAM is a target (slave), dbus is initiator (master)
 515         fanouts = ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
 516         fanins = ['dat_r', 'ack', 'err']
 517         for fanout in fanouts:
 518             print("fanout", fanout, getattr(sram.bus, fanout).shape(),
 519                   getattr(dbus, fanout).shape())
 520             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
 521             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
 522         for fanin in fanins:
 523             comb += getattr(dbus, fanin).eq(getattr(sram.bus, fanin))
 524         # connect address
 525         comb += sram.bus.adr.eq(dbus.adr)
 526
 527         return m
 528