1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
, InternalOp
, CryIn
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.test
.common
import TestCase
16 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
20 def get_cu_inputs(dec2
, sim
):
21 """naming (res) must conform to LDSTFunctionUnit input regspec
26 reg1_ok
= yield dec2
.e
.read_reg1
.ok
28 data1
= yield dec2
.e
.read_reg1
.data
29 res
['ra'] = sim
.gpr(data1
).value
32 reg2_ok
= yield dec2
.e
.read_reg2
.ok
34 data2
= yield dec2
.e
.read_reg2
.data
35 res
['rb'] = sim
.gpr(data2
).value
38 reg3_ok
= yield dec2
.e
.read_reg3
.ok
40 data3
= yield dec2
.e
.read_reg3
.data
41 res
['rc'] = sim
.gpr(data3
).value
44 oe
= yield dec2
.e
.oe
.data
[0] & dec2
.e
.oe
.ok
46 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
52 class LDSTTestCase(FHDLTestCase
):
55 def __init__(self
, name
):
56 super().__init
__(name
)
59 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None):
60 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
)
61 self
.test_data
.append(tc
)
63 def test_load_store(self
):
66 initial_regs
= [0] * 32
67 initial_regs
[1] = 0x0004
68 initial_regs
[2] = 0x0008
69 self
.run_tst_program(Program(lst
), initial_regs
)
72 pspec
= LDSTPipeSpec(id_wid
=2)
73 alu
= LDSTBasePipe(pspec
)
74 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
75 with
open("ldst_pipeline.il", "w") as f
: