src/soc/fu/logical/input_stage.py

   1 # This stage is intended to adjust the input data before sending it to
   2 # the actual Logical pipeline. Things like handling inverting the input, xer_ca
   3 # generation for subtraction, and handling of immediates should happen
   4 # here
   5 from soc.fu.common_input_stage import CommonInputStage
   6 from soc.fu.logical.pipe_data import LogicalInputData
   7
   8
   9 class LogicalInputStage(CommonInputStage):
  10     def __init__(self, pspec):
  11         super().__init__(pspec, "input")
  12         self.invert_op = "rb" # inversion is on register b
  13
  14     def ispec(self):
  15         return LogicalInputData(self.pspec)
  16
  17     def ospec(self):
  18         return LogicalInputData(self.pspec)
  19
  20     def elaborate(self, platform):
  21         m = super().elaborate(platform) # covers B-invert, carry, excludes SO
  22         comb = m.d.comb
  23         ctx = self.i.ctx
  24
  25         return m