add input / output stage missing modules
[soc.git] / src / soc / fu / logical / input_stage.py
1 # This stage is intended to adjust the input data before sending it to
2 # the actual Logical pipeline. Things like handling inverting the input, xer_ca
3 # generation for subtraction, and handling of immediates should happen
4 # here
5 from soc.fu.common_input_stage import CommonInputStage
6 from soc.fu.logical.pipe_data import LogicalInputData
7
8
9 class LogicalInputStage(CommonInputStage):
10 def __init__(self, pspec):
11 super().__init__(pspec, "input")
12
13 def ispec(self):
14 return LogicalInputData(self.pspec)
15
16 def ospec(self):
17 return LogicalInputData(self.pspec)
18
19 def elaborate(self, platform):
20 m = super().elaborate(platform) # covers A-invert, carry, excludes SO
21 comb = m.d.comb
22 ctx = self.i.ctx
23
24 # operand b
25 comb += self.o.b.eq(self.i.b)
26
27 return m