1 # This stage is intended to do most of the work of executing Logical
2 # instructions. This is OR, AND, XOR, POPCNT, PRTY, CMPB, BPERMD, CNTLZ
3 # however input and output stages also perform bit-negation on input(s)
4 # and output, as well as carry and overflow generation.
5 # This module however should not gate the carry or overflow, that's up
8 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
9 from nmigen
import (Module
, Signal
, Cat
, Repl
, Mux
, Const
, Array
)
10 from nmutil
.pipemodbase
import PipeModBase
11 from nmutil
.clz
import CLZ
12 from soc
.fu
.logical
.pipe_data
import LogicalInputData
13 from soc
.fu
.logical
.bpermd
import Bpermd
14 from soc
.fu
.logical
.popcount
import Popcount
15 from soc
.fu
.logical
.pipe_data
import LogicalOutputData
16 from ieee754
.part
.partsig
import PartitionedSignal
17 from soc
.decoder
.power_enums
import MicrOp
19 from soc
.decoder
.power_fields
import DecodeFields
20 from soc
.decoder
.power_fieldsn
import SignalBitRange
23 class LogicalMainStage(PipeModBase
):
24 def __init__(self
, pspec
):
25 super().__init
__(pspec
, "main")
26 self
.fields
= DecodeFields(SignalBitRange
, [self
.i
.ctx
.op
.insn
])
27 self
.fields
.create_specs()
30 return LogicalInputData(self
.pspec
)
33 return LogicalOutputData(self
.pspec
)
35 def elaborate(self
, platform
):
38 op
, a
, b
, o
= self
.i
.ctx
.op
, self
.i
.a
, self
.i
.b
, self
.o
.o
40 comb
+= o
.ok
.eq(1) # overridden if no op activates
42 m
.submodules
.bpermd
= bpermd
= Bpermd(64)
43 m
.submodules
.popcount
= popcount
= Popcount()
45 ##########################
46 # main switch for logic ops AND, OR and XOR, cmpb, parity, and popcount
48 with m
.Switch(op
.insn_type
):
51 ###### AND, OR, XOR v3.0B p92-95
53 with m
.Case(MicrOp
.OP_AND
):
54 comb
+= o
.data
.eq(a
& b
)
55 with m
.Case(MicrOp
.OP_OR
):
56 comb
+= o
.data
.eq(a | b
)
57 with m
.Case(MicrOp
.OP_XOR
):
58 comb
+= o
.data
.eq(a ^ b
)
63 with m
.Case(MicrOp
.OP_CMPB
):
66 slc
= slice(i
*8, (i
+1)*8)
67 l
.append(Repl(a
[slc
] == b
[slc
], 8))
68 comb
+= o
.data
.eq(Cat(*l
))
71 ###### popcount v3.0B p97, p98
73 with m
.Case(MicrOp
.OP_POPCNT
):
74 comb
+= popcount
.a
.eq(a
)
75 comb
+= popcount
.b
.eq(b
)
76 comb
+= popcount
.data_len
.eq(op
.data_len
)
77 comb
+= o
.data
.eq(popcount
.o
)
80 ###### parity v3.0B p98
82 with m
.Case(MicrOp
.OP_PRTY
):
83 # strange instruction which XORs together the LSBs of each byte
84 par0
= Signal(reset_less
=True)
85 par1
= Signal(reset_less
=True)
86 comb
+= par0
.eq(Cat(a
[0], a
[8], a
[16], a
[24]).xor())
87 comb
+= par1
.eq(Cat(a
[32], a
[40], a
[48], a
[56]).xor())
88 with m
.If(op
.data_len
[3] == 1):
89 comb
+= o
.data
.eq(par0 ^ par1
)
92 comb
+= o
[32].eq(par1
)
95 ###### cntlz v3.0B p99
97 with m
.Case(MicrOp
.OP_CNTZ
):
98 XO
= self
.fields
.FormX
.XO
[0:-1]
99 count_right
= Signal(reset_less
=True)
100 comb
+= count_right
.eq(XO
[-1])
102 cntz_i
= Signal(64, reset_less
=True)
103 a32
= Signal(32, reset_less
=True)
104 comb
+= a32
.eq(a
[0:32])
106 with m
.If(op
.is_32bit
):
107 comb
+= cntz_i
.eq(Mux(count_right
, a32
[::-1], a32
))
109 comb
+= cntz_i
.eq(Mux(count_right
, a
[::-1], a
))
111 m
.submodules
.clz
= clz
= CLZ(64)
112 comb
+= clz
.sig_in
.eq(cntz_i
)
113 comb
+= o
.data
.eq(Mux(op
.is_32bit
, clz
.lz
-32, clz
.lz
))
116 ###### bpermd v3.0B p100
118 with m
.Case(MicrOp
.OP_BPERM
):
119 comb
+= bpermd
.rs
.eq(a
)
120 comb
+= bpermd
.rb
.eq(b
)
121 comb
+= o
.data
.eq(bpermd
.ra
)
126 ###### sticky overflow and context, both pass-through #####
128 comb
+= self
.o
.xer_so
.data
.eq(self
.i
.xer_so
)
129 comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)