2 Based on microwatt mmu.vhdl
4 * https://bugs.libre-soc.org/show_bug.cgi?id=491
5 * https://bugs.libre-soc.org/show_bug.cgi?id=450
8 from nmigen
import Elaboratable
, Module
, Signal
, Shape
, unsigned
, Cat
, Mux
9 from nmigen
import Record
, Memory
10 from nmigen
import Const
11 from soc
.fu
.mmu
.pipe_data
import MMUInputData
, MMUOutputData
, MMUPipeSpec
12 from nmutil
.singlepipe
import ControlBase
13 from nmutil
.util
import rising_edge
15 from soc
.experiment
.mmu
import MMU
17 from openpower
.consts
import MSR
18 from openpower
.decoder
.power_fields
import DecodeFields
19 from openpower
.decoder
.power_fieldsn
import SignalBitRange
20 from openpower
.decoder
.power_decoder2
import decode_spr_num
21 from openpower
.decoder
.power_enums
import MicrOp
23 from soc
.experiment
.mem_types
import LoadStore1ToMMUType
24 from soc
.experiment
.mem_types
import MMUToLoadStore1Type
26 from soc
.fu
.ldst
.loadstore
import LoadStore1
, TestSRAMLoadStore1
29 class FSMMMUStage(ControlBase
):
32 FSM-based MMU: must call set_ldst_interface and pass in an instance
33 of a LoadStore1. this to comply with the ConfigMemoryPortInterface API
35 this Function Unit is extremely unusual in that it actually stores a
36 "thing" rather than "processes inputs and produces outputs". hence
37 why it has to be a FSM. linking up LD/ST however is going to have
38 to be done back in Issuer (or Core). sorted: call set_ldst_interface
40 def __init__(self
, pspec
):
45 self
.p
.data_i
= MMUInputData(pspec
)
46 self
.n
.data_o
= MMUOutputData(pspec
)
50 # debugging output for gtkw
51 self
.debug0
= Signal(4)
52 self
.illegal
= Signal()
54 # for SPR field number access
56 self
.fields
= DecodeFields(SignalBitRange
, [i
.ctx
.op
.insn
])
57 self
.fields
.create_specs()
59 def set_ldst_interface(self
, ldst
):
60 """must be called back in Core, after FUs have been set up.
61 one of those will be the MMU (us!) but the LoadStore1 instance
62 must be set up in ConfigMemoryPortInterface. sigh.
64 # incoming PortInterface
66 self
.dcache
= self
.ldst
.dcache
67 self
.pi
= self
.ldst
.pi
69 def elaborate(self
, platform
):
70 assert hasattr(self
, "dcache"), "remember to call set_ldst_interface"
71 m
= super().elaborate(platform
)
72 comb
, sync
= m
.d
.comb
, m
.d
.sync
75 # link mmu and dcache together
76 m
.submodules
.mmu
= mmu
= self
.mmu
77 ldst
= self
.ldst
# managed externally: do not add here
78 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
79 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
81 l_in
, l_out
= mmu
.l_in
, mmu
.l_out
82 d_in
, d_out
= dcache
.d_in
, dcache
.d_out
83 wb_out
, wb_in
= dcache
.wb_out
, dcache
.wb_in
85 # link ldst and MMU together
86 comb
+= l_in
.eq(ldst
.l_in
)
87 comb
+= ldst
.l_out
.eq(l_out
)
89 data_i
, data_o
= self
.p
.data_i
, self
.n
.data_o
90 a_i
, b_i
, o
, spr1_o
= data_i
.ra
, data_i
.rb
, data_o
.o
, data_o
.spr1
95 # these are set / got here *ON BEHALF* of LoadStore1
96 dsisr
, dar
= ldst
.dsisr
, ldst
.dar
101 m
.d
.comb
+= self
.n
.valid_o
.eq(busy
& done
)
102 m
.d
.comb
+= self
.p
.ready_o
.eq(~busy
)
104 # take copy of X-Form SPR field
105 x_fields
= self
.fields
.FormXFX
106 spr
= Signal(len(x_fields
.SPR
))
107 comb
+= spr
.eq(decode_spr_num(x_fields
.SPR
))
109 # based on MSR bits, set priv and virt mode. TODO: 32-bit mode
110 comb
+= d_in
.priv_mode
.eq(~msr_i
[MSR
.PR
])
111 comb
+= d_in
.virt_mode
.eq(msr_i
[MSR
.DR
])
112 #comb += d_in.mode_32bit.eq(msr_i[MSR.SF]) # ?? err
114 # ok so we have to "pulse" the MMU (or dcache) rather than
115 # hold the valid hi permanently. guess what this does...
118 m
.d
.comb
+= blip
.eq(rising_edge(m
, valid
))
121 with m
.If(self
.p
.valid_i
):
125 # based on the Micro-Op, we work out which of MMU or DCache
126 # should "action" the operation. one of MMU or DCache gets
127 # enabled ("valid") and we twiddle our thumbs until it
130 # FIXME: properly implement MicrOp.OP_MTSPR and MicrOp.OP_MFSPR
132 with m
.Switch(op
.insn_type
):
133 with m
.Case(MicrOp
.OP_MTSPR
):
134 # despite redirection this FU **MUST** behave exactly
135 # like the SPR FU. this **INCLUDES** updating the SPR
136 # regfile because the CSV file entry for OP_MTSPR
137 # categorically defines and requires the expectation
138 # that the CompUnit **WILL** write to the regfile.
139 comb
+= spr1_o
.data
.eq(a_i
)
140 comb
+= spr1_o
.ok
.eq(1)
141 # subset SPR: first check a few bits
142 # XXX NOTE this must now cover **FOUR** values: this
143 # test might not be adequate. DSISR, DAR, PGTBL and PID
144 # must ALL be covered here.
145 with m
.If(~spr
[9] & ~spr
[5]):
146 comb
+= self
.debug0
.eq(3)
147 #if matched update local cached value
149 sync
+= dsisr
.eq(a_i
[:32])
153 # pass it over to the MMU instead
155 comb
+= self
.debug0
.eq(4)
156 # blip the MMU and wait for it to complete
157 comb
+= valid
.eq(1) # start "pulse"
158 comb
+= l_in
.valid
.eq(blip
) # start
159 comb
+= l_in
.mtspr
.eq(1) # mtspr mode
160 comb
+= l_in
.sprn
.eq(spr
) # which SPR
161 comb
+= l_in
.rs
.eq(a_i
) # incoming operand (RS)
162 comb
+= done
.eq(1) # FIXME l_out.done
164 with m
.Case(MicrOp
.OP_MFSPR
):
165 # subset SPR: first check a few bits
166 #with m.If(~spr[9] & ~spr[5]):
167 # comb += self.debug0.eq(5)
169 # comb += o.data.eq(dsisr)
171 # comb += o.data.eq(dar)
172 #do NOT return cached values
173 comb
+= o
.data
.eq(spr1_i
)
176 # pass it over to the MMU instead
178 # comb += self.debug0.eq(6)
179 # # blip the MMU and wait for it to complete
180 # comb += valid.eq(1) # start "pulse"
181 # comb += l_in.valid.eq(blip) # start
182 # comb += l_in.mtspr.eq(0) # mfspr!=mtspr
183 # comb += l_in.sprn.eq(spr) # which SPR
184 # comb += l_in.rs.eq(a_i) # incoming operand (RS)
185 # comb += o.data.eq(l_out.sprval) # SPR from MMU
186 # comb += o.ok.eq(l_out.done) # only when l_out valid
187 # comb += done.eq(1) # FIXME l_out.done
189 # XXX this one is going to have to go through LDSTCompUnit
190 # because it's LDST that has control over dcache
191 # (through PortInterface). or, another means is devised
192 # so as not to have double-drivers of d_in.valid and addr
194 #with m.Case(MicrOp.OP_DCBZ):
195 # # activate dcbz mode (spec: v3.0B p850)
196 # comb += valid.eq(1) # start "pulse"
197 # comb += d_in.valid.eq(blip) # start
198 # comb += d_in.dcbz.eq(1) # dcbz mode
199 # comb += d_in.addr.eq(a_i + b_i) # addr is (RA|0) + RB
200 # comb += done.eq(d_out.store_done) # TODO
201 # comb += self.debug0.eq(1)
203 with m
.Case(MicrOp
.OP_TLBIE
):
204 # pass TLBIE request to MMU (spec: v3.0B p1034)
205 # note that the spr is *not* an actual spr number, it's
206 # just that those bits happen to match with field bits
208 comb
+= valid
.eq(1) # start "pulse"
209 comb
+= l_in
.valid
.eq(blip
) # start
210 comb
+= l_in
.tlbie
.eq(1) # mtspr mode
211 comb
+= l_in
.sprn
.eq(spr
) # use sprn to send insn bits
212 comb
+= l_in
.addr
.eq(b_i
) # incoming operand (RB)
213 comb
+= done
.eq(l_out
.done
) # zzzz
214 comb
+= self
.debug0
.eq(2)
216 with m
.Case(MicrOp
.OP_ILLEGAL
):
217 comb
+= self
.illegal
.eq(1)
219 with m
.If(self
.n
.ready_i
& self
.n
.valid_o
):