3 see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
5 this module is a key strategic module that links pipeline specifications
6 (soc.fu.*.pipe_data and soc.fo.*.pipeline) to MultiCompUnits. MultiCompUnits
7 know absolutely nothing about the data passing through them: all they know
8 is: how many inputs they need to manage, and how many outputs.
10 regspecs tell MultiCompUnit what the ordering of the inputs is, how many to
11 create, and how to connect them up to the ALU being "managed" by this CompUnit.
14 later (TODO) the Register Files will be connected to MultiCompUnits, and,
15 again, the regspecs will say which Regfile (which type) is connected to
16 which MultiCompUnit port, how wide the connection is, and so on.
19 from nmigen
import Const
20 from soc
.regfile
.regfiles
import XERRegs
, FastRegs
22 def get_regspec_bitwidth(regspec
, srcdest
, idx
):
23 print ("get_regspec_bitwidth", regspec
, srcdest
, idx
)
24 bitspec
= regspec
[srcdest
][idx
]
27 for ranges
in bitspec
[2].split(","):
28 ranges
= ranges
.split(":")
30 if len(ranges
) == 1: # only one bit
33 start
, end
= map(int, ranges
)
39 def __init__(self
, rwid
, n_src
=None, n_dst
=None, name
=None):
41 if isinstance(rwid
, int):
42 # rwid: integer (covers all registers)
43 self
._n
_src
, self
._n
_dst
= n_src
, n_dst
46 self
._n
_src
, self
._n
_dst
= len(rwid
[0]), len(rwid
[1])
48 def _get_dstwid(self
, i
):
49 if isinstance(self
._rwid
, int):
51 return get_regspec_bitwidth(self
._rwid
, 1, i
)
53 def _get_srcwid(self
, i
):
54 if isinstance(self
._rwid
, int):
56 return get_regspec_bitwidth(self
._rwid
, 0, i
)
60 def __init__(self
, rwid
, alu
):
64 * :alu: ALU covered by this regspec
67 self
.alu
= alu
# actual ALU - set as a "submodule" of the CU
69 def get_in_name(self
, i
):
70 return self
.rwid
[0][i
][1]
72 def get_out_name(self
, i
):
73 return self
.rwid
[1][i
][1]
76 if isinstance(self
.rwid
, int): # old - testing - API (rwid is int)
77 return self
.alu
.out
[i
]
78 # regspec-based API: look up variable through regspec thru row number
79 return getattr(self
.alu
.n
.data_o
, self
.get_out_name(i
))
82 if isinstance(self
.rwid
, int): # old - testing - API (rwid is int)
84 # regspec-based API: look up variable through regspec thru row number
85 return getattr(self
.alu
.p
.data_i
, self
.get_in_name(i
))
88 if isinstance(self
.rwid
, int): # old - testing - API (rwid is int)
90 return self
.alu
.p
.data_i
.ctx
.op
93 # function for the relationship between regspecs and Decode2Execute1Type
94 def regspec_decode(e
, regfile
, name
):
97 this function encodes the understanding (relationship) between
98 Regfiles, Computation Units, and the Power ISA Decoder (PowerDecoder2).
100 based on the regspec, which contains the register file name and register
101 name, return a tuple of:
103 * how the decoder should determine whether the Function Unit needs
105 * which Regfile port should be read to get that data
106 * when it comes to writing: likewise, which Regfile port should be written
108 Note that some of the port numbering encoding is *unary*. in the case
109 of "Full Condition Register", it's a full 8-bit mask of read/write-enables.
110 This actually matches directly with the XFX field in MTCR, and at
111 some point that 8-bit mask from the instruction could actually be passed directly through to full_cr (TODO).
113 For the INT and CR numbering, these are expressed in binary in the
114 instruction (note however that XFX in MTCR is unary-masked!)
116 XER is implicitly-encoded based on whether the operation has carry or
119 FAST regfile is, again, implicitly encoded, back in PowerDecode2, based
120 on the type of operation (see DecodeB for an example).
122 The SPR regfile on the other hand is *binary*-encoded, and, furthermore,
123 has to be "remapped".
127 # Int register numbering is *unary* encoded
128 if name
== 'ra': # RA
129 return e
.read_reg1
.ok
, 1<<e
.read_reg1
.data
, None
130 if name
== 'rb': # RB
131 return e
.read_reg2
.ok
, 1<<e
.read_reg2
.data
, None
132 if name
== 'rc': # RS
133 return e
.read_reg3
.ok
, 1<<e
.read_reg3
.data
, None
136 # CRRegs register numbering is *unary* encoded
137 if name
== 'full_cr': # full CR
138 return e
.read_cr_whole
, 0b11111111, 0b11111111
139 if name
== 'cr_a': # CR A
140 return e
.read_cr1
.ok
, 1<<e
.read_cr1
.data
, 1<<e
.write_cr
.data
141 if name
== 'cr_b': # CR B
142 return e
.read_cr2
.ok
, 1<<e
.read_cr2
.data
, None
143 if name
== 'cr_c': # CR C
144 return e
.read_cr3
.ok
, 1<<e
.read_cr2
.data
, None
147 # XERRegs register numbering is *unary* encoded
152 return e
.oe
.oe
& e
.oe
.oe_ok
, SO
, SO
154 return e
.oe
.oe
& e
.oe
.oe_ok
, OV
, OV
156 return e
.input_carry
, CA
, CA
158 if regfile
== 'FAST':
159 # FAST register numbering is *unary* encoded
161 MSR
= 1<<FastRegs
.MSR
162 CTR
= 1<<FastRegs
.CTR
164 TAR
= 1<<FastRegs
.TAR
165 SRR1
= 1<<FastRegs
.SRR1
166 SRR2
= 1<<FastRegs
.SRR2
167 if name
in ['cia', 'nia']:
168 return Const(1), PC
, PC
170 return Const(1), MSR
, MSR
171 # TODO: remap the SPR numbers to FAST regs
173 return e
.read_spr1
.ok
, 1<<e
.read_spr1
.data
, 1<<e
.write_spr
.data
175 return e
.read_spr2
.ok
, 1<<e
.read_spr2
.data
, 1<<e
.write_spr
.data
177 assert False, "regspec not found %s %d" % (repr(regspec
), idx
)