2 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
3 # Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 # This stage is intended to do most of the work of executing shift
6 # instructions, as well as carry and overflow generation. This module
7 # however should not gate the carry or overflow, that's up to the
9 from nmigen
import (Module
, Signal
, Cat
, Repl
, Mux
, Const
)
10 from nmutil
.pipemodbase
import PipeModBase
11 from soc
.fu
.pipe_data
import get_pspec_draft_bitmanip
12 from soc
.fu
.shift_rot
.pipe_data
import (ShiftRotOutputData
,
14 from nmutil
.lut
import BitwiseLut
15 from nmutil
.grev
import GRev
16 from openpower
.decoder
.power_enums
import MicrOp
17 from soc
.fu
.shift_rot
.rotator
import Rotator
19 from openpower
.decoder
.power_fields
import DecodeFields
20 from openpower
.decoder
.power_fieldsn
import SignalBitRange
23 class ShiftRotMainStage(PipeModBase
):
24 def __init__(self
, pspec
):
25 super().__init
__(pspec
, "main")
26 self
.draft_bitmanip
= get_pspec_draft_bitmanip(pspec
)
27 self
.fields
= DecodeFields(SignalBitRange
, [self
.i
.ctx
.op
.insn
])
28 self
.fields
.create_specs()
31 return ShiftRotInputData(self
.pspec
)
34 return ShiftRotOutputData(self
.pspec
)
36 def elaborate(self
, platform
):
44 if self
.draft_bitmanip
:
45 bitwise_lut
= BitwiseLut(input_count
=3, width
=64)
46 m
.submodules
.bitwise_lut
= bitwise_lut
47 comb
+= bitwise_lut
.inputs
[0].eq(self
.i
.rb
)
48 comb
+= bitwise_lut
.inputs
[1].eq(self
.i
.ra
)
49 comb
+= bitwise_lut
.inputs
[2].eq(self
.i
.rc
)
50 # 6 == log2(64) because we have 64-bit values
51 grev
= GRev(log2_width
=6)
52 m
.submodules
.grev
= grev
53 with m
.If(op
.is_32bit
):
54 # 32-bit, so input is lower 32-bits zero-extended
55 comb
+= grev
.input.eq(self
.i
.ra
[0:32])
56 # 32-bit, so we only feed in log2(32) == 5 bits
57 comb
+= grev
.chunk_sizes
.eq(self
.i
.rb
[0:5])
59 comb
+= grev
.input.eq(self
.i
.ra
)
60 comb
+= grev
.chunk_sizes
.eq(self
.i
.rb
)
62 # NOTE: the sh field immediate is read in by PowerDecode2
63 # (actually DecodeRB), whereupon by way of rb "immediate" mode
64 # it ends up in self.i.rb.
66 # obtain me and mb fields from instruction.
67 m_fields
= self
.fields
.instrs
['M']
68 md_fields
= self
.fields
.instrs
['MD']
69 mb
= Signal(m_fields
['MB'][0:-1].shape())
70 me
= Signal(m_fields
['ME'][0:-1].shape())
71 mb_extra
= Signal(1, reset_less
=True)
72 comb
+= mb
.eq(m_fields
['MB'][0:-1])
73 comb
+= me
.eq(m_fields
['ME'][0:-1])
74 comb
+= mb_extra
.eq(md_fields
['mb'][0:-1][0])
76 # set up microwatt rotator module
77 m
.submodules
.rotator
= rotator
= Rotator()
81 rotator
.mb_extra
.eq(mb_extra
),
82 rotator
.rs
.eq(self
.i
.rs
),
83 rotator
.ra
.eq(self
.i
.a
),
84 rotator
.shift
.eq(self
.i
.rb
), # can also be sh (in immediate mode)
85 rotator
.is_32bit
.eq(op
.is_32bit
),
86 rotator
.arith
.eq(op
.is_signed
),
89 comb
+= o
.ok
.eq(1) # defaults to enabled
91 # instruction rotate type
92 mode
= Signal(4, reset_less
=True)
93 comb
+= Cat(rotator
.right_shift
,
96 rotator
.sign_ext_rs
).eq(mode
)
98 # outputs from the microwatt rotator module
99 comb
+= [o
.data
.eq(rotator
.result_o
),
100 self
.o
.xer_ca
.data
.eq(Repl(rotator
.carry_out_o
, 2))]
102 with m
.Switch(op
.insn_type
):
103 with m
.Case(MicrOp
.OP_SHL
):
104 comb
+= mode
.eq(0b0000) # L-shift
105 with m
.Case(MicrOp
.OP_SHR
):
106 comb
+= mode
.eq(0b0001) # R-shift
107 with m
.Case(MicrOp
.OP_RLC
):
108 comb
+= mode
.eq(0b0110) # clear LR
109 with m
.Case(MicrOp
.OP_RLCL
):
110 comb
+= mode
.eq(0b0010) # clear L
111 with m
.Case(MicrOp
.OP_RLCR
):
112 comb
+= mode
.eq(0b0100) # clear R
113 with m
.Case(MicrOp
.OP_EXTSWSLI
):
114 comb
+= mode
.eq(0b1000) # L-ext
115 if self
.draft_bitmanip
:
116 with m
.Case(MicrOp
.OP_TERNLOG
):
117 # TODO: this only works for ternlogi, change to get lut
118 # value from register when we implement other variants
119 comb
+= bitwise_lut
.lut
.eq(self
.fields
.FormTLI
.TLI
[:])
120 comb
+= o
.data
.eq(bitwise_lut
.output
)
121 comb
+= self
.o
.xer_ca
.data
.eq(0)
122 with m
.Case(MicrOp
.OP_GREV
):
123 comb
+= o
.data
.eq(grev
.output
)
124 comb
+= self
.o
.xer_ca
.data
.eq(0)
126 comb
+= o
.ok
.eq(0) # otherwise disable
128 ###### sticky overflow and context, both pass-through #####
130 comb
+= self
.o
.xer_so
.data
.eq(self
.i
.xer_so
)
131 comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)