1 # This stage is intended to handle the gating of carry and overflow
2 # out, summary overflow generation, and updating the condition
4 from soc
.fu
.common_output_stage
import CommonOutputStage
5 from soc
.fu
.shift_rot
.pipe_data
import (ShiftRotOutputData
,
6 ShiftRotOutputDataFinal
)
9 class ShiftRotOutputStage(CommonOutputStage
):
12 return ShiftRotOutputData(self
.pspec
)
15 return ShiftRotOutputDataFinal(self
.pspec
)