src/soc/fu/spr/main_stage.py

   1 """SPR Pipeline
   2
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=348
   4 * https://libre-soc.org/openpower/isa/sprset/
   5 """
   6
   7 from nmigen import (Module, Signal, Cat)
   8 from nmutil.pipemodbase import PipeModBase
   9 from soc.fu.spr.pipe_data import SPRInputData, SPROutputData
  10 from soc.decoder.power_enums import MicrOp, SPR, XER_bits
  11
  12 from soc.decoder.power_fields import DecodeFields
  13 from soc.decoder.power_fieldsn import SignalBitRange
  14 from soc.decoder.power_decoder2 import decode_spr_num
  15
  16
  17 class SPRMainStage(PipeModBase):
  18     def __init__(self, pspec):
  19         super().__init__(pspec, "spr_main")
  20         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  21         self.fields.create_specs()
  22
  23     def ispec(self):
  24         return SPRInputData(self.pspec)
  25
  26     def ospec(self):
  27         return SPROutputData(self.pspec)
  28
  29     def elaborate(self, platform):
  30         m = Module()
  31         comb = m.d.comb
  32         op = self.i.ctx.op
  33
  34         # convenience variables
  35         a_i, spr1_i, fast1_i = self.i.a, self.i.spr1, self.i.fast1
  36         so_i, ov_i, ca_i = self.i.xer_so, self.i.xer_ov, self.i.xer_ca
  37         so_o, ov_o, ca_o = self.o.xer_so, self.o.xer_ov, self.o.xer_ca
  38         o, spr1_o, fast1_o = self.o.o, self.o.spr1, self.o.fast1
  39         state_i, state_o = self.i.state, self.o.state
  40
  41         # take copy of D-Form TO field
  42         x_fields = self.fields.FormXFX
  43         spr = Signal(len(x_fields.SPR))
  44         comb += spr.eq(decode_spr_num(x_fields.SPR))
  45
  46         # TODO: some #defines for the bits n stuff.
  47         with m.Switch(op.insn_type):
  48             #### MTSPR ####
  49             with m.Case(MicrOp.OP_MTSPR):
  50                 with m.Switch(spr):
  51                     # fast SPRs first
  52                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0,
  53                                 SPR.SRR1, SPR.XER):
  54                         comb += fast1_o.data.eq(a_i)
  55                         comb += fast1_o.ok.eq(1)
  56                         # XER is constructed
  57                         with m.If(spr == SPR.XER):
  58                             # sticky
  59                             comb += so_o.data.eq(a_i[63-XER_bits['SO']])
  60                             comb += so_o.ok.eq(1)
  61                             # overflow
  62                             comb += ov_o.data[0].eq(a_i[63-XER_bits['OV']])
  63                             comb += ov_o.data[1].eq(a_i[63-XER_bits['OV32']])
  64                             comb += ov_o.ok.eq(1)
  65                             # carry
  66                             comb += ca_o.data[0].eq(a_i[63-XER_bits['CA']])
  67                             comb += ca_o.data[1].eq(a_i[63-XER_bits['CA32']])
  68                             comb += ca_o.ok.eq(1)
  69                     # STATE SPRs (dec, tb)
  70                     with m.Case(SPR.DEC):
  71                         comb += state_o.data.eq(a_i)
  72                         comb += state_o.ok.eq(1)
  73
  74                     # slow SPRs TODO
  75
  76             # move from SPRs
  77             with m.Case(MicrOp.OP_MFSPR):
  78                 comb += o.ok.eq(1)
  79                 with m.Switch(spr):
  80                     # fast SPRs first
  81                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1,
  82                                 SPR.XER):
  83                         comb += o.data.eq(fast1_i)
  84                         with m.If(spr == SPR.XER):
  85                             # bits 0:31 and 35:43 are treated as reserved
  86                             # and return 0s when read using mfxer
  87                             comb += o[32:64].eq(0)       # MBS0 bits 0-31
  88                             comb += o[63-43:64-35].eq(0) # MSB0 bits 35-43
  89                             # sticky
  90                             comb += o[63-XER_bits['SO']].eq(so_i)
  91                             # overflow
  92                             comb += o[63-XER_bits['OV']].eq(ov_i[0])
  93                             comb += o[63-XER_bits['OV32']].eq(ov_i[1])
  94                             # carry
  95                             comb += o[63-XER_bits['CA']].eq(ca_i[0])
  96                             comb += o[63-XER_bits['CA32']].eq(ca_i[1])
  97                     # STATE SPRs (dec, tb)
  98                     with m.Case(SPR.DEC, SPR.TB):
  99                         comb += o.data.eq(state_i)
 100                     with m.Case(SPR.TBU):
 101                         comb += o.data[0:32].eq(state_i[32:64])
 102
 103                     # slow SPRs TODO
 104
 105         comb += self.o.ctx.eq(self.i.ctx)
 106
 107         return m