src/soc/fu/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 import inspect
   7 import functools
   8 import types
   9 from openpower.decoder.power_enums import XER_bits, CryIn, spr_dict
  10 from soc.regfile.util import fast_reg_to_spr, slow_reg_to_spr  # HACK!
  11 from soc.regfile.regfiles import XERRegs, FastRegs
  12
  13
  14 # TODO: make this a util routine (somewhere)
  15 def mask_extend(x, nbits, repeat):
  16     res = 0
  17     extended = (1<<repeat)-1
  18     for i in range(nbits):
  19         if x & (1<<i):
  20             res |= extended << (i*repeat)
  21     return res
  22
  23
  24 class SkipCase(Exception):
  25     """Raise this exception to skip a test case.
  26
  27     Usually you'd use one of the skip_case* decorators.
  28
  29     For use with TestAccumulatorBase
  30     """
  31
  32
  33 def _id(obj):
  34     """identity function"""
  35     return obj
  36
  37
  38 def skip_case(reason):
  39     """
  40     Unconditionally skip a test case.
  41
  42     Use like:
  43         @skip_case("my reason for skipping")
  44         def case_abc(self):
  45             ...
  46     or:
  47         @skip_case
  48         def case_def(self):
  49             ...
  50
  51     For use with TestAccumulatorBase
  52     """
  53     def decorator(item):
  54         assert not isinstance(item, type), \
  55             "can't use skip_case to decorate types"
  56
  57         @functools.wraps(item)
  58         def wrapper(*args, **kwargs):
  59             raise SkipCase(reason)
  60         return wrapper
  61     if isinstance(reason, types.FunctionType):
  62         item = reason
  63         reason = ""
  64         return decorator(item)
  65     return decorator
  66
  67
  68 def skip_case_if(condition, reason):
  69     """
  70     Conditionally skip a test case.
  71
  72     Use like:
  73         @skip_case_if(should_i_skip(), "my reason for skipping")
  74         def case_abc(self):
  75             ...
  76
  77     For use with TestAccumulatorBase
  78     """
  79     if condition:
  80         return skip_case(reason)
  81     return _id
  82
  83
  84 class TestAccumulatorBase:
  85
  86     def __init__(self):
  87         self.test_data = []
  88         # automatically identifies anything starting with "case_" and
  89         # runs it.  very similar to unittest auto-identification except
  90         # we need a different system
  91         for n, v in self.__class__.__dict__.items():
  92             if n.startswith("case_") and callable(v):
  93                 try:
  94                     v(self)
  95                 except SkipCase as e:
  96                     # TODO(programmerjake): translate to final test sending
  97                     # skip signal to unittest. for now, just print the skipped
  98                     # reason and ignore
  99                     print(f"SKIPPED({n}):", str(e))
 100
 101     def add_case(self, prog, initial_regs=None, initial_sprs=None,
 102                  initial_cr=0, initial_msr=0,
 103                  initial_mem=None,
 104                  initial_svstate=0):
 105
 106         test_name = inspect.stack()[1][3]  # name of caller of this function
 107         tc = TestCase(prog, test_name,
 108                       regs=initial_regs, sprs=initial_sprs, cr=initial_cr,
 109                       msr=initial_msr,
 110                       mem=initial_mem,
 111                       svstate=initial_svstate)
 112
 113         self.test_data.append(tc)
 114
 115
 116 class TestCase:
 117     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
 118                  msr=0,
 119                  do_sim=True,
 120                  extra_break_addr=None,
 121                  svstate=0):
 122
 123         self.program = program
 124         self.name = name
 125
 126         if regs is None:
 127             regs = [0] * 32
 128         if sprs is None:
 129             sprs = {}
 130         if mem is None:
 131             mem = {}
 132         self.regs = regs
 133         self.sprs = sprs
 134         self.cr = cr
 135         self.mem = mem
 136         self.msr = msr
 137         self.do_sim = do_sim
 138         self.extra_break_addr = extra_break_addr
 139         self.svstate = svstate
 140
 141
 142 class ALUHelpers:
 143
 144     def get_sim_fast_reg(res, sim, dec2, reg, name):
 145         spr_sel = fast_reg_to_spr(reg)
 146         spr_data = sim.spr[spr_sel].value
 147         res[name] = spr_data
 148
 149     def get_sim_cia(res, sim, dec2):
 150         res['cia'] = sim.pc.CIA.value
 151
 152     # use this *after* the simulation has run a step (it returns CIA)
 153     def get_sim_nia(res, sim, dec2):
 154         res['nia'] = sim.pc.CIA.value
 155
 156     def get_sim_msr(res, sim, dec2):
 157         res['msr'] = sim.msr.value
 158
 159     def get_sim_slow_spr1(res, sim, dec2):
 160         spr1_en = yield dec2.e.read_spr1.ok
 161         if spr1_en:
 162             spr1_sel = yield dec2.e.read_spr1.data
 163             spr1_sel = slow_reg_to_spr(spr1_sel)
 164             spr1_data = sim.spr[spr1_sel].value
 165             res['spr1'] = spr1_data
 166
 167     def get_sim_fast_spr1(res, sim, dec2):
 168         fast1_en = yield dec2.e.read_fast1.ok
 169         if fast1_en:
 170             fast1_sel = yield dec2.e.read_fast1.data
 171             spr1_sel = fast_reg_to_spr(fast1_sel)
 172             spr1_data = sim.spr[spr1_sel].value
 173             res['fast1'] = spr1_data
 174
 175     def get_sim_fast_spr2(res, sim, dec2):
 176         fast2_en = yield dec2.e.read_fast2.ok
 177         if fast2_en:
 178             fast2_sel = yield dec2.e.read_fast2.data
 179             spr2_sel = fast_reg_to_spr(fast2_sel)
 180             spr2_data = sim.spr[spr2_sel].value
 181             res['fast2'] = spr2_data
 182
 183     def get_sim_cr_a(res, sim, dec2):
 184         cridx_ok = yield dec2.e.read_cr1.ok
 185         if cridx_ok:
 186             cridx = yield dec2.e.read_cr1.data
 187             res['cr_a'] = sim.crl[cridx].get_range().value
 188
 189     def get_sim_cr_b(res, sim, dec2):
 190         cridx_ok = yield dec2.e.read_cr2.ok
 191         if cridx_ok:
 192             cridx = yield dec2.e.read_cr2.data
 193             res['cr_b'] = sim.crl[cridx].get_range().value
 194
 195     def get_sim_cr_c(res, sim, dec2):
 196         cridx_ok = yield dec2.e.read_cr3.ok
 197         if cridx_ok:
 198             cridx = yield dec2.e.read_cr3.data
 199             res['cr_c'] = sim.crl[cridx].get_range().value
 200
 201     def get_sim_int_ra(res, sim, dec2):
 202         # TODO: immediate RA zero
 203         reg1_ok = yield dec2.e.read_reg1.ok
 204         if reg1_ok:
 205             data1 = yield dec2.e.read_reg1.data
 206             res['ra'] = sim.gpr(data1).value
 207
 208     def get_sim_int_rb(res, sim, dec2):
 209         reg2_ok = yield dec2.e.read_reg2.ok
 210         if reg2_ok:
 211             data = yield dec2.e.read_reg2.data
 212             res['rb'] = sim.gpr(data).value
 213
 214     def get_sim_int_rc(res, sim, dec2):
 215         reg3_ok = yield dec2.e.read_reg3.ok
 216         if reg3_ok:
 217             data = yield dec2.e.read_reg3.data
 218             res['rc'] = sim.gpr(data).value
 219
 220     def get_rd_sim_xer_ca(res, sim, dec2):
 221         cry_in = yield dec2.e.do.input_carry
 222         xer_in = yield dec2.e.xer_in
 223         if (xer_in & (1<<XERRegs.CA)) or cry_in == CryIn.CA.value:
 224             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 225             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 226             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 227
 228     def set_int_ra(alu, dec2, inp):
 229         # TODO: immediate RA zero.
 230         if 'ra' in inp:
 231             yield alu.p.data_i.ra.eq(inp['ra'])
 232         else:
 233             yield alu.p.data_i.ra.eq(0)
 234
 235     def set_int_rb(alu, dec2, inp):
 236         yield alu.p.data_i.rb.eq(0)
 237         if 'rb' in inp:
 238             yield alu.p.data_i.rb.eq(inp['rb'])
 239         if not hasattr(dec2.e.do, "imm_data"):
 240             return
 241         # If there's an immediate, set the B operand to that
 242         imm_ok = yield dec2.e.do.imm_data.ok
 243         if imm_ok:
 244             data2 = yield dec2.e.do.imm_data.data
 245             yield alu.p.data_i.rb.eq(data2)
 246
 247     def set_int_rc(alu, dec2, inp):
 248         if 'rc' in inp:
 249             yield alu.p.data_i.rc.eq(inp['rc'])
 250         else:
 251             yield alu.p.data_i.rc.eq(0)
 252
 253     def set_xer_ca(alu, dec2, inp):
 254         if 'xer_ca' in inp:
 255             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
 256             print("extra inputs: CA/32", bin(inp['xer_ca']))
 257
 258     def set_xer_ov(alu, dec2, inp):
 259         if 'xer_ov' in inp:
 260             yield alu.p.data_i.xer_ov.eq(inp['xer_ov'])
 261             print("extra inputs: OV/32", bin(inp['xer_ov']))
 262
 263     def set_xer_so(alu, dec2, inp):
 264         if 'xer_so' in inp:
 265             so = inp['xer_so']
 266             print("extra inputs: so", so)
 267             yield alu.p.data_i.xer_so.eq(so)
 268
 269     def set_msr(alu, dec2, inp):
 270         print("TODO: deprecate set_msr")
 271         if 'msr' in inp:
 272             yield alu.p.data_i.msr.eq(inp['msr'])
 273
 274     def set_cia(alu, dec2, inp):
 275         print("TODO: deprecate set_cia")
 276         if 'cia' in inp:
 277             yield alu.p.data_i.cia.eq(inp['cia'])
 278
 279     def set_slow_spr1(alu, dec2, inp):
 280         if 'spr1' in inp:
 281             yield alu.p.data_i.spr1.eq(inp['spr1'])
 282
 283     def set_slow_spr2(alu, dec2, inp):
 284         if 'spr2' in inp:
 285             yield alu.p.data_i.spr2.eq(inp['spr2'])
 286
 287     def set_fast_spr1(alu, dec2, inp):
 288         if 'fast1' in inp:
 289             yield alu.p.data_i.fast1.eq(inp['fast1'])
 290
 291     def set_fast_spr2(alu, dec2, inp):
 292         if 'fast2' in inp:
 293             yield alu.p.data_i.fast2.eq(inp['fast2'])
 294
 295     def set_cr_a(alu, dec2, inp):
 296         if 'cr_a' in inp:
 297             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 298
 299     def set_cr_b(alu, dec2, inp):
 300         if 'cr_b' in inp:
 301             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 302
 303     def set_cr_c(alu, dec2, inp):
 304         if 'cr_c' in inp:
 305             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 306
 307     def set_full_cr(alu, dec2, inp):
 308         if 'full_cr' in inp:
 309             full_reg = yield dec2.dec_cr_in.whole_reg.data
 310             full_reg_ok = yield dec2.dec_cr_in.whole_reg.ok
 311             full_cr_mask = mask_extend(full_reg, 8, 4)
 312             yield alu.p.data_i.full_cr.eq(inp['full_cr'] & full_cr_mask)
 313         else:
 314             yield alu.p.data_i.full_cr.eq(0)
 315
 316     def get_slow_spr1(res, alu, dec2):
 317         spr1_valid = yield alu.n.data_o.spr1.ok
 318         if spr1_valid:
 319             res['spr1'] = yield alu.n.data_o.spr1.data
 320
 321     def get_slow_spr2(res, alu, dec2):
 322         spr2_valid = yield alu.n.data_o.spr2.ok
 323         if spr2_valid:
 324             res['spr2'] = yield alu.n.data_o.spr2.data
 325
 326     def get_fast_spr1(res, alu, dec2):
 327         spr1_valid = yield alu.n.data_o.fast1.ok
 328         if spr1_valid:
 329             res['fast1'] = yield alu.n.data_o.fast1.data
 330
 331     def get_fast_spr2(res, alu, dec2):
 332         spr2_valid = yield alu.n.data_o.fast2.ok
 333         if spr2_valid:
 334             res['fast2'] = yield alu.n.data_o.fast2.data
 335
 336     def get_cia(res, alu, dec2):
 337         res['cia'] = yield alu.p.data_i.cia
 338
 339     def get_nia(res, alu, dec2):
 340         nia_valid = yield alu.n.data_o.nia.ok
 341         if nia_valid:
 342             res['nia'] = yield alu.n.data_o.nia.data
 343
 344     def get_msr(res, alu, dec2):
 345         msr_valid = yield alu.n.data_o.msr.ok
 346         if msr_valid:
 347             res['msr'] = yield alu.n.data_o.msr.data
 348
 349     def get_int_o1(res, alu, dec2):
 350         out_reg_valid = yield dec2.e.write_ea.ok
 351         if out_reg_valid:
 352             res['o1'] = yield alu.n.data_o.o1.data
 353
 354     def get_int_o(res, alu, dec2):
 355         out_reg_valid = yield dec2.e.write_reg.ok
 356         if out_reg_valid:
 357             res['o'] = yield alu.n.data_o.o.data
 358
 359     def get_cr_a(res, alu, dec2):
 360         cridx_ok = yield dec2.e.write_cr.ok
 361         if cridx_ok:
 362             res['cr_a'] = yield alu.n.data_o.cr0.data
 363
 364     def get_xer_so(res, alu, dec2):
 365         oe = yield dec2.e.do.oe.oe
 366         oe_ok = yield dec2.e.do.oe.ok
 367         xer_out = yield dec2.e.xer_out
 368         if not (yield alu.n.data_o.xer_so.ok):
 369             return
 370         if xer_out or (oe and oe_ok):
 371             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 372
 373     def get_xer_ov(res, alu, dec2):
 374         oe = yield dec2.e.do.oe.oe
 375         oe_ok = yield dec2.e.do.oe.ok
 376         xer_out = yield dec2.e.xer_out
 377         if not (yield alu.n.data_o.xer_ov.ok):
 378             return
 379         if xer_out or (oe and oe_ok):
 380             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 381
 382     def get_xer_ca(res, alu, dec2):
 383         cry_out = yield dec2.e.do.output_carry
 384         xer_out = yield dec2.e.xer_out
 385         if not (yield alu.n.data_o.xer_ca.ok):
 386             return
 387         if xer_out or (cry_out):
 388             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 389
 390     def get_sim_int_o(res, sim, dec2):
 391         out_reg_valid = yield dec2.e.write_reg.ok
 392         if out_reg_valid:
 393             write_reg_idx = yield dec2.e.write_reg.data
 394             res['o'] = sim.gpr(write_reg_idx).value
 395
 396     def get_sim_int_o1(res, sim, dec2):
 397         out_reg_valid = yield dec2.e.write_ea.ok
 398         if out_reg_valid:
 399             write_reg_idx = yield dec2.e.write_ea.data
 400             res['o1'] = sim.gpr(write_reg_idx).value
 401
 402     def get_wr_sim_cr_a(res, sim, dec2):
 403         cridx_ok = yield dec2.e.write_cr.ok
 404         if cridx_ok:
 405             cridx = yield dec2.e.write_cr.data
 406             res['cr_a'] = sim.crl[cridx].get_range().value
 407
 408     def get_wr_fast_spr2(res, sim, dec2):
 409         ok = yield dec2.e.write_fast2.ok
 410         if ok:
 411             spr_num = yield dec2.e.write_fast2.data
 412             spr_num = fast_reg_to_spr(spr_num)
 413             spr_name = spr_dict[spr_num].SPR
 414             res['fast2'] = sim.spr[spr_name].value
 415
 416     def get_wr_fast_spr1(res, sim, dec2):
 417         ok = yield dec2.e.write_fast1.ok
 418         if ok:
 419             spr_num = yield dec2.e.write_fast1.data
 420             spr_num = fast_reg_to_spr(spr_num)
 421             spr_name = spr_dict[spr_num].SPR
 422             res['fast1'] = sim.spr[spr_name].value
 423
 424     def get_wr_slow_spr1(res, sim, dec2):
 425         ok = yield dec2.e.write_spr.ok
 426         if ok:
 427             spr_num = yield dec2.e.write_spr.data
 428             spr_num = slow_reg_to_spr(spr_num)
 429             spr_name = spr_dict[spr_num].SPR
 430             res['spr1'] = sim.spr[spr_name].value
 431
 432     def get_wr_sim_xer_ca(res, sim, dec2):
 433         # if not (yield alu.n.data_o.xer_ca.ok):
 434         #    return
 435         cry_out = yield dec2.e.do.output_carry
 436         xer_out = yield dec2.e.xer_out
 437         if cry_out or xer_out:
 438             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 439             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 440             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 441
 442     def get_wr_sim_xer_ov(res, sim, alu, dec2):
 443         oe = yield dec2.e.do.oe.oe
 444         oe_ok = yield dec2.e.do.oe.ok
 445         xer_out = yield dec2.e.xer_out
 446         print("get_wr_sim_xer_ov", xer_out)
 447         if not (yield alu.n.data_o.xer_ov.ok):
 448             return
 449         if xer_out or (oe and oe_ok):
 450             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 451             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 452             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 453
 454     def get_wr_sim_xer_so(res, sim, alu, dec2):
 455         oe = yield dec2.e.do.oe.oe
 456         oe_ok = yield dec2.e.do.oe.ok
 457         xer_out = yield dec2.e.xer_out
 458         if not (yield alu.n.data_o.xer_so.ok):
 459             return
 460         if xer_out or (oe and oe_ok):
 461             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 462
 463     def get_sim_xer_ov(res, sim, dec2):
 464         oe = yield dec2.e.do.oe.oe
 465         oe_ok = yield dec2.e.do.oe.ok
 466         xer_in = yield dec2.e.xer_in
 467         print("get_sim_xer_ov", xer_in)
 468         if (xer_in & (1<<XERRegs.OV)) or (oe and oe_ok):
 469             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 470             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 471             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 472
 473     def get_sim_xer_so(res, sim, dec2):
 474         print ("XER", sim.spr.__class__, sim.spr, sim.spr['XER'])
 475         oe = yield dec2.e.do.oe.oe
 476         oe_ok = yield dec2.e.do.oe.ok
 477         xer_in = yield dec2.e.xer_in
 478         rc = yield dec2.e.do.rc.rc
 479         rc_ok = yield dec2.e.do.rc.ok
 480         if (xer_in & (1<<XERRegs.SO)) or (oe and oe_ok) or (rc and rc_ok):
 481             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 482
 483     def check_slow_spr1(dut, res, sim_o, msg):
 484         if 'spr1' in res:
 485             expected = sim_o['spr1']
 486             alu_out = res['spr1']
 487             print(f"expected {expected:x}, actual: {alu_out:x}")
 488             dut.assertEqual(expected, alu_out, msg)
 489
 490     def check_fast_spr1(dut, res, sim_o, msg):
 491         if 'fast1' in res:
 492             expected = sim_o['fast1']
 493             alu_out = res['fast1']
 494             print(f"expected {expected:x}, actual: {alu_out:x}")
 495             dut.assertEqual(expected, alu_out, msg)
 496
 497     def check_fast_spr2(dut, res, sim_o, msg):
 498         if 'fast2' in res:
 499             expected = sim_o['fast2']
 500             alu_out = res['fast2']
 501             print(f"expected {expected:x}, actual: {alu_out:x}")
 502             dut.assertEqual(expected, alu_out, msg)
 503
 504     def check_int_o1(dut, res, sim_o, msg):
 505         if 'o1' in res:
 506             expected = sim_o['o1']
 507             alu_out = res['o1']
 508             print(f"expected {expected:x}, actual: {alu_out:x}")
 509             dut.assertEqual(expected, alu_out, msg)
 510
 511     def check_int_o(dut, res, sim_o, msg):
 512         if 'o' in res:
 513             expected = sim_o['o']
 514             alu_out = res['o']
 515             print(f"expected int sim {expected:x}, actual: {alu_out:x}")
 516             dut.assertEqual(expected, alu_out, msg)
 517
 518     def check_msr(dut, res, sim_o, msg):
 519         if 'msr' in res:
 520             expected = sim_o['msr']
 521             alu_out = res['msr']
 522             print(f"expected {expected:x}, actual: {alu_out:x}")
 523             dut.assertEqual(expected, alu_out, msg)
 524
 525     def check_nia(dut, res, sim_o, msg):
 526         if 'nia' in res:
 527             expected = sim_o['nia']
 528             alu_out = res['nia']
 529             print(f"expected {expected:x}, actual: {alu_out:x}")
 530             dut.assertEqual(expected, alu_out, msg)
 531
 532     def check_cr_a(dut, res, sim_o, msg):
 533         if 'cr_a' in res:
 534             cr_expected = sim_o['cr_a']
 535             cr_actual = res['cr_a']
 536             print("CR", cr_expected, cr_actual)
 537             dut.assertEqual(cr_expected, cr_actual, msg)
 538
 539     def check_xer_ca(dut, res, sim_o, msg):
 540         if 'xer_ca' in res:
 541             ca_expected = sim_o['xer_ca']
 542             ca_actual = res['xer_ca']
 543             print("CA", ca_expected, ca_actual)
 544             dut.assertEqual(ca_expected, ca_actual, msg)
 545
 546     def check_xer_ov(dut, res, sim_o, msg):
 547         if 'xer_ov' in res:
 548             ov_expected = sim_o['xer_ov']
 549             ov_actual = res['xer_ov']
 550             print("OV", ov_expected, ov_actual)
 551             dut.assertEqual(ov_expected, ov_actual, msg)
 552
 553     def check_xer_so(dut, res, sim_o, msg):
 554         if 'xer_so' in res:
 555             so_expected = sim_o['xer_so']
 556             so_actual = res['xer_so']
 557             print("SO", so_expected, so_actual)
 558             dut.assertEqual(so_expected, so_actual, msg)