src/soc/fu/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 from soc.decoder.power_enums import XER_bits
   7 from soc.regfile.util import fast_reg_to_spr # HACK!
   8
   9
  10 class TestCase:
  11     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
  12                        msr=0):
  13
  14         self.program = program
  15         self.name = name
  16
  17         if regs is None:
  18             regs = [0] * 32
  19         if sprs is None:
  20             sprs = {}
  21         if mem is None:
  22             mem = {}
  23         self.regs = regs
  24         self.sprs = sprs
  25         self.cr = cr
  26         self.mem = mem
  27         self.msr = msr
  28
  29 class ALUHelpers:
  30
  31     def get_sim_fast_spr1(res, sim, dec2):
  32         fast1_en = yield dec2.e.read_fast1.ok
  33         if fast1_en:
  34             fast1_sel = yield dec2.e.read_fast1.data
  35             spr1_sel = fast_reg_to_spr(fast1_sel)
  36             spr1_data = sim.spr[spr1_sel].value
  37             res['spr1'] = spr1_data
  38
  39     def get_sim_fast_spr2(res, sim, dec2):
  40         fast2_en = yield dec2.e.read_fast2.ok
  41         if fast2_en:
  42             fast2_sel = yield dec2.e.read_fast2.data
  43             spr2_sel = fast_reg_to_spr(fast2_sel)
  44             spr2_data = sim.spr[spr2_sel].value
  45             res['spr2'] = spr2_data
  46
  47     def get_sim_cr_a(res, sim, dec2):
  48         cridx_ok = yield dec2.e.read_cr1.ok
  49         if cridx_ok:
  50             cridx = yield dec2.e.read_cr1.data
  51             res['cr_a'] = sim.crl[cridx].get_range().value
  52
  53     def get_sim_int_ra(res, sim, dec2):
  54         # TODO: immediate RA zero
  55         reg1_ok = yield dec2.e.read_reg1.ok
  56         if reg1_ok:
  57             data1 = yield dec2.e.read_reg1.data
  58             res['ra'] = sim.gpr(data1).value
  59
  60     def get_sim_int_rb(res, sim, dec2):
  61         reg2_ok = yield dec2.e.read_reg2.ok
  62         if reg2_ok:
  63             data = yield dec2.e.read_reg2.data
  64             res['rb'] = sim.gpr(data).value
  65
  66     def set_int_ra(alu, dec2, inp):
  67         # TODO: immediate RA zero.
  68         if 'ra' in inp:
  69             yield alu.p.data_i.ra.eq(inp['ra'])
  70         else:
  71             yield alu.p.data_i.ra.eq(0)
  72
  73     def set_int_rb(alu, dec2, inp):
  74         yield alu.p.data_i.rb.eq(0)
  75         if 'rb' in inp:
  76             yield alu.p.data_i.rb.eq(inp['rb'])
  77         # If there's an immediate, set the B operand to that
  78         imm_ok = yield dec2.e.imm_data.imm_ok
  79         if imm_ok:
  80             data2 = yield dec2.e.imm_data.imm
  81             yield alu.p.data_i.rb.eq(data2)
  82
  83     def set_int_rc(alu, dec2, inp):
  84         if 'rc' in inp:
  85             yield alu.p.data_i.rc.eq(inp['rc'])
  86         else:
  87             yield alu.p.data_i.rc.eq(0)
  88
  89     def set_xer_ca(alu, dec2, inp):
  90         if 'xer_ca' in inp:
  91             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
  92             print ("extra inputs: CA/32", bin(inp['xer_ca']))
  93
  94     def set_xer_so(alu, dec2, inp):
  95         if 'xer_so' in inp:
  96             so = inp['xer_so']
  97             print ("extra inputs: so", so)
  98             yield alu.p.data_i.xer_so.eq(so)
  99
 100     def set_fast_cia(alu, dec2, inp):
 101         if 'cia' in inp:
 102             yield alu.p.data_i.cia.eq(inp['cia'])
 103
 104     def set_fast_spr1(alu, dec2, inp):
 105         if 'spr1' in inp:
 106             yield alu.p.data_i.spr1.eq(inp['spr1'])
 107
 108     def set_fast_spr2(alu, dec2, inp):
 109         if 'spr2' in inp:
 110             yield alu.p.data_i.spr2.eq(inp['spr2'])
 111
 112     def set_cr_a(alu, dec2, inp):
 113         if 'cr_a' in inp:
 114             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 115
 116     def set_cr_b(alu, dec2, inp):
 117         if 'cr_b' in inp:
 118             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 119
 120     def set_cr_c(alu, dec2, inp):
 121         if 'cr_c' in inp:
 122             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 123
 124     def set_full_cr(alu, dec2, inp):
 125         if 'full_cr' in inp:
 126             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
 127         else:
 128             yield alu.p.data_i.full_cr.eq(0)
 129
 130     def get_int_o(res, alu, dec2):
 131         out_reg_valid = yield dec2.e.write_reg.ok
 132         if out_reg_valid:
 133             res['o'] = yield alu.n.data_o.o.data
 134
 135     def get_cr_a(res, alu, dec2):
 136         cridx_ok = yield dec2.e.write_cr.ok
 137         if cridx_ok:
 138             res['cr_a'] = yield alu.n.data_o.cr0.data
 139
 140     def get_xer_so(res, alu, dec2):
 141         oe = yield dec2.e.oe.oe
 142         oe_ok = yield dec2.e.oe.ok
 143         if oe and oe_ok:
 144             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 145
 146     def get_xer_ov(res, alu, dec2):
 147         oe = yield dec2.e.oe.oe
 148         oe_ok = yield dec2.e.oe.ok
 149         if oe and oe_ok:
 150             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 151
 152     def get_xer_ca(res, alu, dec2):
 153         cry_out = yield dec2.e.output_carry
 154         if cry_out:
 155             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 156
 157     def get_sim_int_o(res, sim, dec2):
 158         out_reg_valid = yield dec2.e.write_reg.ok
 159         if out_reg_valid:
 160             write_reg_idx = yield dec2.e.write_reg.data
 161             res['o'] = sim.gpr(write_reg_idx).value
 162
 163     def get_wr_sim_cr_a(res, sim, dec2):
 164         cridx_ok = yield dec2.e.write_cr.ok
 165         if cridx_ok:
 166             cridx = yield dec2.e.write_cr.data
 167             res['cr_a'] = sim.crl[cridx].get_range().value
 168
 169     def get_sim_xer_ca(res, sim, dec2):
 170         cry_out = yield dec2.e.output_carry
 171         if cry_out:
 172             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 173             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 174             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 175
 176     def get_sim_xer_ov(res, sim, dec2):
 177         oe = yield dec2.e.oe.oe
 178         oe_ok = yield dec2.e.oe.ok
 179         if oe and oe_ok:
 180             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 181             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 182             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 183
 184     def get_sim_xer_so(res, sim, dec2):
 185         oe = yield dec2.e.oe.oe
 186         oe_ok = yield dec2.e.oe.ok
 187         if oe and oe_ok:
 188             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 189
 190     def check_int_o(dut, res, sim_o, msg):
 191         if 'o' in res:
 192             expected = sim_o['o']
 193             alu_out = res['o']
 194             print(f"expected {expected:x}, actual: {alu_out:x}")
 195             dut.assertEqual(expected, alu_out, msg)
 196
 197     def check_cr_a(dut, res, sim_o, msg):
 198         if 'cr_a' in res:
 199             cr_expected = sim_o['cr_a']
 200             cr_actual = res['cr_a']
 201             print ("CR", cr_expected, cr_actual)
 202             dut.assertEqual(cr_expected, cr_actual, msg)
 203
 204     def check_xer_ca(dut, res, sim_o, msg):
 205         if 'xer_ca' in res:
 206             ca_expected = sim_o['xer_ca']
 207             ca_actual = res['xer_ca']
 208             print ("CA", ca_expected, ca_actual)
 209             dut.assertEqual(ca_expected, ca_actual, msg)
 210
 211     def check_xer_ov(dut, res, sim_o, msg):
 212         if 'xer_ov' in res:
 213             ov_expected = sim_o['xer_ov']
 214             ov_actual = res['xer_ov']
 215             print ("OV", ov_expected, ov_actual)
 216             dut.assertEqual(ov_expected, ov_actual, msg)
 217
 218     def check_xer_so(dut, res, sim_o, msg):
 219         if 'xer_so' in res:
 220             so_expected = sim_o['xer_so']
 221             so_actual = res['xer_so']
 222             print ("SO", so_expected, so_actual)
 223             dut.assertEqual(so_expected, so_actual, msg)
 224