src/soc/fu/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 import inspect
   7 import functools
   8 import types
   9 from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
  10 from soc.regfile.util import fast_reg_to_spr  # HACK!
  11 from soc.regfile.regfiles import FastRegs
  12
  13
  14 class SkipCase(Exception):
  15     """Raise this exception to skip a test case.
  16
  17     Usually you'd use one of the skip_case* decorators.
  18
  19     For use with TestAccumulatorBase
  20     """
  21
  22
  23 def _id(obj):
  24     """identity function"""
  25     return obj
  26
  27
  28 def skip_case(reason):
  29     """
  30     Unconditionally skip a test case.
  31
  32     Use like:
  33         @skip_case("my reason for skipping")
  34         def case_abc(self):
  35             ...
  36     or:
  37         @skip_case
  38         def case_def(self):
  39             ...
  40
  41     For use with TestAccumulatorBase
  42     """
  43     def decorator(item):
  44         assert not isinstance(item, type), \
  45             "can't use skip_case to decorate types"
  46
  47         @functools.wraps(item)
  48         def wrapper(*args, **kwargs):
  49             raise SkipCase(reason)
  50         return wrapper
  51     if isinstance(reason, types.FunctionType):
  52         item = reason
  53         reason = ""
  54         return decorator(item)
  55     return decorator
  56
  57
  58 def skip_case_if(condition, reason):
  59     """
  60     Conditionally skip a test case.
  61
  62     Use like:
  63         @skip_case_if(should_i_skip(), "my reason for skipping")
  64         def case_abc(self):
  65             ...
  66
  67     For use with TestAccumulatorBase
  68     """
  69     if condition:
  70         return skip_case(reason)
  71     return _id
  72
  73
  74 class TestAccumulatorBase:
  75
  76     def __init__(self):
  77         self.test_data = []
  78         # automatically identifies anything starting with "case_" and
  79         # runs it.  very similar to unittest auto-identification except
  80         # we need a different system
  81         for n, v in self.__class__.__dict__.items():
  82             if n.startswith("case_") and callable(v):
  83                 try:
  84                     v(self)
  85                 except SkipCase as e:
  86                     # TODO(programmerjake): translate to final test sending
  87                     # skip signal to unittest. for now, just print the skipped
  88                     # reason and ignore
  89                     print(f"SKIPPED({n}):", str(e))
  90
  91     def add_case(self, prog, initial_regs=None, initial_sprs=None,
  92                  initial_cr=0, initial_msr=0,
  93                  initial_mem=None):
  94
  95         test_name = inspect.stack()[1][3]  # name of caller of this function
  96         tc = TestCase(prog, test_name,
  97                       regs=initial_regs, sprs=initial_sprs, cr=initial_cr,
  98                       msr=initial_msr,
  99                       mem=initial_mem)
 100
 101         self.test_data.append(tc)
 102
 103
 104 class TestCase:
 105     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
 106                  msr=0,
 107                  do_sim=True,
 108                  extra_break_addr=None):
 109
 110         self.program = program
 111         self.name = name
 112
 113         if regs is None:
 114             regs = [0] * 32
 115         if sprs is None:
 116             sprs = {}
 117         if mem is None:
 118             mem = {}
 119         self.regs = regs
 120         self.sprs = sprs
 121         self.cr = cr
 122         self.mem = mem
 123         self.msr = msr
 124         self.do_sim = do_sim
 125         self.extra_break_addr = extra_break_addr
 126
 127
 128 class ALUHelpers:
 129
 130     def get_sim_fast_reg(res, sim, dec2, reg, name):
 131         spr_sel = fast_reg_to_spr(reg)
 132         spr_data = sim.spr[spr_sel].value
 133         res[name] = spr_data
 134
 135     def get_sim_cia(res, sim, dec2):
 136         res['cia'] = sim.pc.CIA.value
 137
 138     # use this *after* the simulation has run a step (it returns CIA)
 139     def get_sim_nia(res, sim, dec2):
 140         res['nia'] = sim.pc.CIA.value
 141
 142     def get_sim_msr(res, sim, dec2):
 143         res['msr'] = sim.msr.value
 144
 145     def get_sim_slow_spr1(res, sim, dec2):
 146         spr1_en = yield dec2.e.read_spr1.ok
 147         if spr1_en:
 148             spr1_sel = yield dec2.e.read_spr1.data
 149             spr1_data = sim.spr[spr1_sel].value
 150             res['spr1'] = spr1_data
 151
 152     def get_sim_fast_spr1(res, sim, dec2):
 153         fast1_en = yield dec2.e.read_fast1.ok
 154         if fast1_en:
 155             fast1_sel = yield dec2.e.read_fast1.data
 156             spr1_sel = fast_reg_to_spr(fast1_sel)
 157             spr1_data = sim.spr[spr1_sel].value
 158             res['fast1'] = spr1_data
 159
 160     def get_sim_fast_spr2(res, sim, dec2):
 161         fast2_en = yield dec2.e.read_fast2.ok
 162         if fast2_en:
 163             fast2_sel = yield dec2.e.read_fast2.data
 164             spr2_sel = fast_reg_to_spr(fast2_sel)
 165             spr2_data = sim.spr[spr2_sel].value
 166             res['fast2'] = spr2_data
 167
 168     def get_sim_cr_a(res, sim, dec2):
 169         cridx_ok = yield dec2.e.read_cr1.ok
 170         if cridx_ok:
 171             cridx = yield dec2.e.read_cr1.data
 172             res['cr_a'] = sim.crl[cridx].get_range().value
 173
 174     def get_sim_int_ra(res, sim, dec2):
 175         # TODO: immediate RA zero
 176         reg1_ok = yield dec2.e.read_reg1.ok
 177         if reg1_ok:
 178             data1 = yield dec2.e.read_reg1.data
 179             res['ra'] = sim.gpr(data1).value
 180
 181     def get_sim_int_rb(res, sim, dec2):
 182         reg2_ok = yield dec2.e.read_reg2.ok
 183         if reg2_ok:
 184             data = yield dec2.e.read_reg2.data
 185             res['rb'] = sim.gpr(data).value
 186
 187     def get_sim_int_rc(res, sim, dec2):
 188         reg3_ok = yield dec2.e.read_reg3.ok
 189         if reg3_ok:
 190             data = yield dec2.e.read_reg3.data
 191             res['rc'] = sim.gpr(data).value
 192
 193     def get_rd_sim_xer_ca(res, sim, dec2):
 194         cry_in = yield dec2.e.do.input_carry
 195         xer_in = yield dec2.e.xer_in
 196         if xer_in or cry_in == CryIn.CA.value:
 197             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 198             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 199             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 200
 201     def set_int_ra(alu, dec2, inp):
 202         # TODO: immediate RA zero.
 203         if 'ra' in inp:
 204             yield alu.p.data_i.ra.eq(inp['ra'])
 205         else:
 206             yield alu.p.data_i.ra.eq(0)
 207
 208     def set_int_rb(alu, dec2, inp):
 209         yield alu.p.data_i.rb.eq(0)
 210         if 'rb' in inp:
 211             yield alu.p.data_i.rb.eq(inp['rb'])
 212         # If there's an immediate, set the B operand to that
 213         imm_ok = yield dec2.e.do.imm_data.imm_ok
 214         if imm_ok:
 215             data2 = yield dec2.e.do.imm_data.imm
 216             yield alu.p.data_i.rb.eq(data2)
 217
 218     def set_int_rc(alu, dec2, inp):
 219         if 'rc' in inp:
 220             yield alu.p.data_i.rc.eq(inp['rc'])
 221         else:
 222             yield alu.p.data_i.rc.eq(0)
 223
 224     def set_xer_ca(alu, dec2, inp):
 225         if 'xer_ca' in inp:
 226             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
 227             print("extra inputs: CA/32", bin(inp['xer_ca']))
 228
 229     def set_xer_ov(alu, dec2, inp):
 230         if 'xer_ov' in inp:
 231             yield alu.p.data_i.xer_ov.eq(inp['xer_ov'])
 232             print("extra inputs: OV/32", bin(inp['xer_ov']))
 233
 234     def set_xer_so(alu, dec2, inp):
 235         if 'xer_so' in inp:
 236             so = inp['xer_so']
 237             print("extra inputs: so", so)
 238             yield alu.p.data_i.xer_so.eq(so)
 239
 240     def set_msr(alu, dec2, inp):
 241         print("TODO: deprecate set_msr")
 242         if 'msr' in inp:
 243             yield alu.p.data_i.msr.eq(inp['msr'])
 244
 245     def set_cia(alu, dec2, inp):
 246         print("TODO: deprecate set_cia")
 247         if 'cia' in inp:
 248             yield alu.p.data_i.cia.eq(inp['cia'])
 249
 250     def set_slow_spr1(alu, dec2, inp):
 251         if 'spr1' in inp:
 252             yield alu.p.data_i.spr1.eq(inp['spr1'])
 253
 254     def set_slow_spr2(alu, dec2, inp):
 255         if 'spr2' in inp:
 256             yield alu.p.data_i.spr2.eq(inp['spr2'])
 257
 258     def set_fast_spr1(alu, dec2, inp):
 259         if 'fast1' in inp:
 260             yield alu.p.data_i.fast1.eq(inp['fast1'])
 261
 262     def set_fast_spr2(alu, dec2, inp):
 263         if 'fast2' in inp:
 264             yield alu.p.data_i.fast2.eq(inp['fast2'])
 265
 266     def set_cr_a(alu, dec2, inp):
 267         if 'cr_a' in inp:
 268             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 269
 270     def set_cr_b(alu, dec2, inp):
 271         if 'cr_b' in inp:
 272             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 273
 274     def set_cr_c(alu, dec2, inp):
 275         if 'cr_c' in inp:
 276             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 277
 278     def set_full_cr(alu, dec2, inp):
 279         if 'full_cr' in inp:
 280             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
 281         else:
 282             yield alu.p.data_i.full_cr.eq(0)
 283
 284     def get_slow_spr1(res, alu, dec2):
 285         spr1_valid = yield alu.n.data_o.spr1.ok
 286         if spr1_valid:
 287             res['spr1'] = yield alu.n.data_o.spr1.data
 288
 289     def get_slow_spr2(res, alu, dec2):
 290         spr2_valid = yield alu.n.data_o.spr2.ok
 291         if spr2_valid:
 292             res['spr2'] = yield alu.n.data_o.spr2.data
 293
 294     def get_fast_spr1(res, alu, dec2):
 295         spr1_valid = yield alu.n.data_o.fast1.ok
 296         if spr1_valid:
 297             res['fast1'] = yield alu.n.data_o.fast1.data
 298
 299     def get_fast_spr2(res, alu, dec2):
 300         spr2_valid = yield alu.n.data_o.fast2.ok
 301         if spr2_valid:
 302             res['fast2'] = yield alu.n.data_o.fast2.data
 303
 304     def get_cia(res, alu, dec2):
 305         res['cia'] = yield alu.p.data_i.cia
 306
 307     def get_nia(res, alu, dec2):
 308         nia_valid = yield alu.n.data_o.nia.ok
 309         if nia_valid:
 310             res['nia'] = yield alu.n.data_o.nia.data
 311
 312     def get_msr(res, alu, dec2):
 313         msr_valid = yield alu.n.data_o.msr.ok
 314         if msr_valid:
 315             res['msr'] = yield alu.n.data_o.msr.data
 316
 317     def get_int_o1(res, alu, dec2):
 318         out_reg_valid = yield dec2.e.write_ea.ok
 319         if out_reg_valid:
 320             res['o1'] = yield alu.n.data_o.o1.data
 321
 322     def get_int_o(res, alu, dec2):
 323         out_reg_valid = yield dec2.e.write_reg.ok
 324         if out_reg_valid:
 325             res['o'] = yield alu.n.data_o.o.data
 326
 327     def get_cr_a(res, alu, dec2):
 328         cridx_ok = yield dec2.e.write_cr.ok
 329         if cridx_ok:
 330             res['cr_a'] = yield alu.n.data_o.cr0.data
 331
 332     def get_xer_so(res, alu, dec2):
 333         oe = yield dec2.e.do.oe.oe
 334         oe_ok = yield dec2.e.do.oe.ok
 335         xer_out = yield dec2.e.xer_out
 336         if not (yield alu.n.data_o.xer_so.ok):
 337             return
 338         if xer_out or (oe and oe_ok):
 339             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 340
 341     def get_xer_ov(res, alu, dec2):
 342         oe = yield dec2.e.do.oe.oe
 343         oe_ok = yield dec2.e.do.oe.ok
 344         xer_out = yield dec2.e.xer_out
 345         if not (yield alu.n.data_o.xer_ov.ok):
 346             return
 347         if xer_out or (oe and oe_ok):
 348             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 349
 350     def get_xer_ca(res, alu, dec2):
 351         cry_out = yield dec2.e.do.output_carry
 352         xer_out = yield dec2.e.xer_out
 353         if not (yield alu.n.data_o.xer_ca.ok):
 354             return
 355         if xer_out or (cry_out):
 356             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 357
 358     def get_sim_int_o(res, sim, dec2):
 359         out_reg_valid = yield dec2.e.write_reg.ok
 360         if out_reg_valid:
 361             write_reg_idx = yield dec2.e.write_reg.data
 362             res['o'] = sim.gpr(write_reg_idx).value
 363
 364     def get_sim_int_o1(res, sim, dec2):
 365         out_reg_valid = yield dec2.e.write_ea.ok
 366         if out_reg_valid:
 367             write_reg_idx = yield dec2.e.write_ea.data
 368             res['o1'] = sim.gpr(write_reg_idx).value
 369
 370     def get_wr_sim_cr_a(res, sim, dec2):
 371         cridx_ok = yield dec2.e.write_cr.ok
 372         if cridx_ok:
 373             cridx = yield dec2.e.write_cr.data
 374             res['cr_a'] = sim.crl[cridx].get_range().value
 375
 376     def get_wr_fast_spr2(res, sim, dec2):
 377         ok = yield dec2.e.write_fast2.ok
 378         if ok:
 379             spr_num = yield dec2.e.write_fast2.data
 380             spr_num = fast_reg_to_spr(spr_num)
 381             spr_name = spr_dict[spr_num].SPR
 382             res['fast2'] = sim.spr[spr_name].value
 383
 384     def get_wr_fast_spr1(res, sim, dec2):
 385         ok = yield dec2.e.write_fast1.ok
 386         if ok:
 387             spr_num = yield dec2.e.write_fast1.data
 388             spr_num = fast_reg_to_spr(spr_num)
 389             spr_name = spr_dict[spr_num].SPR
 390             res['fast1'] = sim.spr[spr_name].value
 391
 392     def get_wr_slow_spr1(res, sim, dec2):
 393         ok = yield dec2.e.write_spr.ok
 394         if ok:
 395             spr_num = yield dec2.e.write_spr.data
 396             spr_name = spr_dict[spr_num].SPR
 397             res['spr1'] = sim.spr[spr_name].value
 398
 399     def get_wr_sim_xer_ca(res, sim, dec2):
 400         # if not (yield alu.n.data_o.xer_ca.ok):
 401         #    return
 402         cry_out = yield dec2.e.do.output_carry
 403         xer_out = yield dec2.e.xer_out
 404         if cry_out or xer_out:
 405             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 406             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 407             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 408
 409     def get_wr_sim_xer_ov(res, sim, alu, dec2):
 410         oe = yield dec2.e.do.oe.oe
 411         oe_ok = yield dec2.e.do.oe.ok
 412         xer_out = yield dec2.e.xer_out
 413         print("get_wr_sim_xer_ov", xer_out)
 414         if not (yield alu.n.data_o.xer_ov.ok):
 415             return
 416         if xer_out or (oe and oe_ok):
 417             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 418             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 419             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 420
 421     def get_wr_sim_xer_so(res, sim, alu, dec2):
 422         oe = yield dec2.e.do.oe.oe
 423         oe_ok = yield dec2.e.do.oe.ok
 424         xer_out = yield dec2.e.xer_out
 425         if not (yield alu.n.data_o.xer_so.ok):
 426             return
 427         if xer_out or (oe and oe_ok):
 428             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 429
 430     def get_sim_xer_ov(res, sim, dec2):
 431         oe = yield dec2.e.do.oe.oe
 432         oe_ok = yield dec2.e.do.oe.ok
 433         xer_in = yield dec2.e.xer_in
 434         print("get_sim_xer_ov", xer_in)
 435         if xer_in or (oe and oe_ok):
 436             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 437             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 438             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 439
 440     def get_sim_xer_so(res, sim, dec2):
 441         yield
 442         #oe = yield dec2.e.do.oe.oe
 443         #oe_ok = yield dec2.e.do.oe.ok
 444         #xer_in = yield dec2.e.xer_in
 445         #if xer_in or (oe and oe_ok):
 446         res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 447
 448     def check_slow_spr1(dut, res, sim_o, msg):
 449         if 'spr1' in res:
 450             expected = sim_o['spr1']
 451             alu_out = res['spr1']
 452             print(f"expected {expected:x}, actual: {alu_out:x}")
 453             dut.assertEqual(expected, alu_out, msg)
 454
 455     def check_fast_spr1(dut, res, sim_o, msg):
 456         if 'fast1' in res:
 457             expected = sim_o['fast1']
 458             alu_out = res['fast1']
 459             print(f"expected {expected:x}, actual: {alu_out:x}")
 460             dut.assertEqual(expected, alu_out, msg)
 461
 462     def check_fast_spr2(dut, res, sim_o, msg):
 463         if 'fast2' in res:
 464             expected = sim_o['fast2']
 465             alu_out = res['fast2']
 466             print(f"expected {expected:x}, actual: {alu_out:x}")
 467             dut.assertEqual(expected, alu_out, msg)
 468
 469     def check_int_o1(dut, res, sim_o, msg):
 470         if 'o1' in res:
 471             expected = sim_o['o1']
 472             alu_out = res['o1']
 473             print(f"expected {expected:x}, actual: {alu_out:x}")
 474             dut.assertEqual(expected, alu_out, msg)
 475
 476     def check_int_o(dut, res, sim_o, msg):
 477         if 'o' in res:
 478             expected = sim_o['o']
 479             alu_out = res['o']
 480             print(f"expected int sim {expected:x}, actual: {alu_out:x}")
 481             dut.assertEqual(expected, alu_out, msg)
 482
 483     def check_msr(dut, res, sim_o, msg):
 484         if 'msr' in res:
 485             expected = sim_o['msr']
 486             alu_out = res['msr']
 487             print(f"expected {expected:x}, actual: {alu_out:x}")
 488             dut.assertEqual(expected, alu_out, msg)
 489
 490     def check_nia(dut, res, sim_o, msg):
 491         if 'nia' in res:
 492             expected = sim_o['nia']
 493             alu_out = res['nia']
 494             print(f"expected {expected:x}, actual: {alu_out:x}")
 495             dut.assertEqual(expected, alu_out, msg)
 496
 497     def check_cr_a(dut, res, sim_o, msg):
 498         if 'cr_a' in res:
 499             cr_expected = sim_o['cr_a']
 500             cr_actual = res['cr_a']
 501             print("CR", cr_expected, cr_actual)
 502             dut.assertEqual(cr_expected, cr_actual, msg)
 503
 504     def check_xer_ca(dut, res, sim_o, msg):
 505         if 'xer_ca' in res:
 506             ca_expected = sim_o['xer_ca']
 507             ca_actual = res['xer_ca']
 508             print("CA", ca_expected, ca_actual)
 509             dut.assertEqual(ca_expected, ca_actual, msg)
 510
 511     def check_xer_ov(dut, res, sim_o, msg):
 512         if 'xer_ov' in res:
 513             ov_expected = sim_o['xer_ov']
 514             ov_actual = res['xer_ov']
 515             print("OV", ov_expected, ov_actual)
 516             dut.assertEqual(ov_expected, ov_actual, msg)
 517
 518     def check_xer_so(dut, res, sim_o, msg):
 519         if 'xer_so' in res:
 520             so_expected = sim_o['xer_so']
 521             so_actual = res['xer_so']
 522             print("SO", so_expected, so_actual)
 523             dut.assertEqual(so_expected, so_actual, msg)