src/soc/fu/trap/main_stage.py

   1
   2 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
   3 from nmutil.pipemodbase import PipeModBase
   4 from nmutil.clz import CLZ
   5 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
   6 from soc.decoder.power_enums import InternalOp
   7
   8 from soc.decoder.power_fields import DecodeFields
   9 from soc.decoder.power_fieldsn import SignalBitRange
  10
  11
  12 def array_of(count, bitwidth):
  13     res = []
  14     for i in range(count):
  15         res.append(Signal(bitwidth, reset_less=True))
  16     return res
  17
  18
  19 class LogicalMainStage(PipeModBase):
  20     def __init__(self, pspec):
  21         super().__init__(pspec, "main")
  22         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  23         self.fields.create_specs()
  24
  25     def ispec(self):
  26         return TrapInputData(self.pspec)
  27
  28     def ospec(self):
  29         return TrapOutputData(self.pspec)
  30
  31     def elaborate(self, platform):
  32         m = Module()
  33         comb = m.d.comb
  34         op, a, b = self.i.ctx.op, self.i.a, self.i.b
  35
  36
  37         comb += self.o.ctx.eq(self.i.ctx)
  38
  39         return m