src/soc/fu/trap/main_stage.py

   1
   2 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, signed)
   3 from nmutil.pipemodbase import PipeModBase
   4 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
   5 from soc.decoder.power_enums import InternalOp
   6
   7 from soc.decoder.power_fields import DecodeFields
   8 from soc.decoder.power_fieldsn import SignalBitRange
   9
  10
  11 class TrapMainStage(PipeModBase):
  12     def __init__(self, pspec):
  13         super().__init__(pspec, "main")
  14         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  15         self.fields.create_specs()
  16
  17     def ispec(self):
  18         return TrapInputData(self.pspec)
  19
  20     def ospec(self):
  21         return TrapOutputData(self.pspec)
  22
  23     def elaborate(self, platform):
  24         m = Module()
  25         comb = m.d.comb
  26         op = self.i.ctx.op
  27
  28         # take copy of D-Form TO field
  29         i_fields = self.fields.FormD
  30         to = Signal(i_fields.TO[0:-1].shape())
  31         comb += to.eq(i_fields.TO[0:-1])
  32
  33         # signed/unsigned temporaries for RA and RB
  34         a_s = Signal(signed(64), reset_less=True)
  35         b_s = Signal(signed(64), reset_less=True)
  36
  37         a = Signal(64, reset_less=True)
  38         b = Signal(64, reset_less=True)
  39
  40         # set up A and B comparison (truncate/sign-extend if 32 bit)
  41         with m.If(op.is_32bit):
  42             comb += a_s.eq(self.i.a[0:32], Repl(self.i.a[32], 32))
  43             comb += b_s.eq(self.i.b[0:32], Repl(self.i.b[32], 32))
  44             comb += a.eq(self.i.a[0:32])
  45             comb += b.eq(self.i.b[0:32])
  46         with m.Else():
  47             comb += a_s.eq(self.i.a)
  48             comb += b_s.eq(self.i.b)
  49             comb += a.eq(self.i.a)
  50             comb += b.eq(self.i.b)
  51
  52         # establish comparison bits
  53         lt_s = Signal(reset_less=True)
  54         gt_s = Signal(reset_less=True)
  55         lt_u = Signal(reset_less=True)
  56         gt_u = Signal(reset_less=True)
  57         equal = Signal(reset_less=True)
  58
  59         comb += lt_s.eq(a_s < b_s)
  60         comb += gt_s.eq(a_s > b_s)
  61         comb += lt_u.eq(a < b)
  62         comb += gt_u.eq(a > b)
  63         comb += equal.eq(a == b)
  64
  65         # They're in reverse bit order because POWER.
  66         # Check V3.0B Book 1, Appendix C.6 for chart
  67         trap_bits = Signal(5)
  68         comb += trap_bits.eq(Cat(gt_u, lt_u, equal, gt_s, lt_s))
  69
  70         # establish if the trap should go ahead (any tests requested in TO)
  71         should_trap = Signal()
  72         comb += should_trap.eq((trap_bits & to).any())
  73
  74         # TODO: some #defines for the bits n stuff.
  75         with m.Switch(op):
  76             with m.Case(InternalOp.OP_TRAP):
  77                 with m.If(should_trap):
  78                     comb += self.o.nia.data.eq(0x700)         # trap address
  79                     comb += self.o.nia.ok.eq(1)
  80                     comb += self.o.srr1.data.eq(self.i.msr)   # old MSR
  81                     comb += self.o.srr1[63-46].eq(1)     # XXX which bit?
  82                     comb += self.o.srr1.ok.eq(1)
  83                     comb += self.o.srr0.data.eq(self.i.cia)   # old PC
  84                     comb += self.o.srr0.ok.eq(1)
  85
  86         comb += self.o.ctx.eq(self.i.ctx)
  87
  88         return m