1 # this file has been generated by sv2nmigen
3 from nmigen
import Signal
, Module
, Const
, Cat
, Elaboratable
6 class axi4_b_buffer(Elaboratable
):
9 self
.axi4_aclk
= Signal() # input
10 self
.axi4_arstn
= Signal() # input
11 self
.s_axi4_bid
= Signal(AXI_ID_WIDTH
) # output
12 self
.s_axi4_bresp
= Signal(2) # output
13 self
.s_axi4_bvalid
= Signal() # output
14 self
.s_axi4_buser
= Signal(AXI_USER_WIDTH
) # output
15 self
.s_axi4_bready
= Signal() # input
16 self
.m_axi4_bid
= Signal(AXI_ID_WIDTH
) # input
17 self
.m_axi4_bresp
= Signal(2) # input
18 self
.m_axi4_bvalid
= Signal() # input
19 self
.m_axi4_buser
= Signal(AXI_USER_WIDTH
) # input
20 self
.m_axi4_bready
= Signal() # output
22 def elaborate(self
, platform
=None):
24 m
.d
.comb
+= self
.None.eq(self
.m_axi4_bresp
)
25 m
.d
.comb
+= self
.None.eq(self
.m_axi4_bid
)
26 m
.d
.comb
+= self
.None.eq(self
.m_axi4_buser
)
27 m
.d
.comb
+= self
.s_axi4_buser
.eq(self
.None)
28 m
.d
.comb
+= self
.s_axi4_bid
.eq(self
.None)
29 m
.d
.comb
+= self
.s_axi4_bresp
.eq(self
.None)
32 # // Copyright 2018 ETH Zurich and University of Bologna.
33 # // Copyright and related rights are licensed under the Solderpad Hardware
34 # // License, Version 0.51 (the "License"); you may not use this file except in
35 # // compliance with the License. You may obtain a copy of the License at
36 # // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
37 # // or agreed to in writing, software, hardware and materials distributed under
38 # // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
39 # // CONDITIONS OF ANY KIND, either express or implied. See the License for the
40 # // specific language governing permissions and limitations under the License.
42 # module axi4_b_buffer
44 # parameter AXI_ID_WIDTH = 4,
45 # parameter AXI_USER_WIDTH = 4
48 # input logic axi4_aclk,
49 # input logic axi4_arstn,
51 # output logic [AXI_ID_WIDTH-1:0] s_axi4_bid,
52 # output logic [1:0] s_axi4_bresp,
53 # output logic s_axi4_bvalid,
54 # output logic [AXI_USER_WIDTH-1:0] s_axi4_buser,
55 # input logic s_axi4_bready,
57 # input logic [AXI_ID_WIDTH-1:0] m_axi4_bid,
58 # input logic [1:0] m_axi4_bresp,
59 # input logic m_axi4_bvalid,
60 # input logic [AXI_USER_WIDTH-1:0] m_axi4_buser,
61 # output logic m_axi4_bready
64 # wire [AXI_ID_WIDTH+AXI_USER_WIDTH+1:0] data_in;
65 # wire [AXI_ID_WIDTH+AXI_USER_WIDTH+1:0] data_out;
67 # assign data_in [1:0] = m_axi4_bresp;
68 # assign data_in [AXI_ID_WIDTH+1:2] = m_axi4_bid;
69 # assign data_in[AXI_ID_WIDTH+AXI_USER_WIDTH+1:AXI_ID_WIDTH+2] = m_axi4_buser;
71 # assign s_axi4_buser = data_out[AXI_ID_WIDTH+AXI_USER_WIDTH+1:AXI_ID_WIDTH+2];
72 # assign s_axi4_bid = data_out[AXI_ID_WIDTH+1:2];
73 # assign s_axi4_bresp = data_out[1:0];
77 # .DATA_WIDTH ( AXI_ID_WIDTH+AXI_USER_WIDTH+2 ),
83 # .rstn ( axi4_arstn ),
84 # .valid_out( s_axi4_bvalid ),
85 # .data_out ( data_out ),
86 # .ready_in ( s_axi4_bready ),
87 # .valid_in ( m_axi4_bvalid ),
88 # .data_in ( data_in ),
89 # .ready_out( m_axi4_bready )