src/soc/litex/florent/libresoc/ls180.py

   1 #
   2 # This file is part of LiteX.
   3 #
   4 # Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   5 # SPDX-License-Identifier: BSD-2-Clause
   6
   7 """ls180 ASIC platform
   8
   9 conceptually similar to the following:
  10
  11 * https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py
  12 * https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py
  13
  14 Total I/O pins: 84.
  15 Fits in a JEDEC QFP-100
  16
  17 """
  18
  19 from migen.fhdl.structure import _Fragment
  20 from litex.build.generic_platform import (GenericPlatform, Pins,
  21                                         Subsignal, IOStandard, Misc,
  22                                         )
  23 from libresoc.ls180io import make_uart, make_gpio
  24 import os
  25
  26
  27 # IOs ----------------------------------------------------------------------------------------------
  28
  29 _io = [
  30     # CLK/RST: 2 pins
  31     ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
  32     ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
  33
  34     # JTAG0: 4 pins
  35     ("jtag", 0,
  36         Subsignal("tms", Pins("Z1"), IOStandard("LVCMOS33")),
  37         Subsignal("tck", Pins("Z2"), IOStandard("LVCMOS33")),
  38         Subsignal("tdi", Pins("Z3"), IOStandard("LVCMOS33")),
  39         Subsignal("tdo", Pins("Z4"), IOStandard("LVCMOS33")),
  40     ),
  41
  42     # I2C0: 2 pins
  43     ("i2c", 0,
  44         Subsignal("scl", Pins("L4"), IOStandard("LVCMOS33")),
  45         Subsignal("sda", Pins("M1"), IOStandard("LVCMOS33"))
  46     ),
  47
  48     # SPI0: 4 pins
  49     ("spi_master", 0,
  50         Subsignal("clk",  Pins("J1")),
  51         Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
  52         Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
  53         Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
  54         Misc("SLEWRATE=FAST"),
  55         IOStandard("LVCMOS33"),
  56     ),
  57
  58     # SPICARD0: 4 pins
  59     ("spisdcard", 0,
  60         Subsignal("clk",  Pins("J1")),
  61         Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
  62         Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
  63         Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
  64         Misc("SLEWRATE=FAST"),
  65         IOStandard("LVCMOS33"),
  66     ),
  67
  68     # SDCARD0: 6 pins
  69     ("sdcard", 0,
  70         Subsignal("clk",  Pins("J1")),
  71         Subsignal("cmd_i",  Pins("J3"), Misc("PULLMODE=UP")),
  72         Subsignal("cmd_o",  Pins("J3"), Misc("PULLMODE=UP")),
  73         Subsignal("cmd_oe",  Pins("J3"), Misc("PULLMODE=UP")),
  74         Subsignal("data_i", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
  75         Subsignal("data_o", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
  76         Subsignal("data_oe", Pins("K2"), Misc("PULLMODE=UP")),
  77         Misc("SLEWRATE=FAST"),
  78         IOStandard("LVCMOS33"),
  79     ),
  80
  81     # SDRAM: 39 pins
  82     ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
  83     ("sdram", 0,
  84         Subsignal("a",     Pins(
  85             "M20 M19 L20 L19 K20 K19 K18 J20",
  86             "J19 H20 N19 G20 G19")),
  87         Subsignal("dq_i",    Pins(
  88             "J16 L18 M18 N18 P18 T18 T17 U20",
  89             "E19 D20 D19 C20 E18 F18 J18 J17")),
  90         Subsignal("dq_o",    Pins(
  91             "J16 L18 M18 N18 P18 T18 T17 U20",
  92             "E19 D20 D19 C20 E18 F18 J18 J17")),
  93         Subsignal("dq_oe",    Pins("J17")),
  94         Subsignal("we_n",  Pins("T20")),
  95         Subsignal("ras_n", Pins("R20")),
  96         Subsignal("cas_n", Pins("T19")),
  97         Subsignal("cs_n",  Pins("P30")),
  98         Subsignal("cke",   Pins("F21")),
  99         Subsignal("ba",    Pins("P19 N20")),
 100         Subsignal("dm",    Pins("U19 E20")),
 101         IOStandard("LVCMOS33"),
 102         Misc("SLEWRATE=FAST"),
 103     ),
 104
 105     # PWM: 2 pins
 106     ("pwm", 0, Pins("P1"), IOStandard("LVCMOS33")),
 107     ("pwm", 1, Pins("P2"), IOStandard("LVCMOS33")),
 108 ]
 109
 110 n_gpio = 16
 111
 112 # 16 GPIOs
 113 _io.append( make_gpio("gpio", 0, n_gpio) )
 114
 115 # EINT: 3 pins
 116 _io.append( ("eint", 0, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) )
 117
 118 # UART0: 2 pins
 119 _io.append(make_uart("uart", 0))
 120 # UART1: 2 pins
 121 _io.append(make_uart("uart", 1))
 122
 123 # not connected - eurgh have to adjust this to match the total pincount.
 124 num_nc = 42
 125 nc = ' '.join("NC%d" % i for i in range(num_nc))
 126 _io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33")))
 127
 128 # Platform -----------------------------------------------------------------------------------------
 129
 130 class LS180Platform(GenericPlatform):
 131     default_clk_name   = "sys_clk"
 132     default_clk_period = 1e9/50e6
 133
 134     def __init__(self, device="LS180", **kwargs):
 135         assert device in ["LS180"]
 136         GenericPlatform.__init__(self, device, _io, **kwargs)
 137
 138     def build(self, fragment,
 139                     build_dir      = "build",
 140                     build_name     = "top",
 141                     run            = True,
 142                     timingstrict   = True,
 143                     **kwargs):
 144
 145         platform = self
 146
 147         # Create build directory
 148         os.makedirs(build_dir, exist_ok=True)
 149         cwd = os.getcwd()
 150         os.chdir(build_dir)
 151
 152         # Finalize design
 153         if not isinstance(fragment, _Fragment):
 154             fragment = fragment.get_fragment()
 155         platform.finalize(fragment)
 156
 157         # Generate verilog
 158         v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
 159         named_sc, named_pc = platform.resolve_signals(v_output.ns)
 160         v_file = build_name + ".v"
 161         v_output.write(v_file)
 162         platform.add_source(v_file)
 163
 164         os.chdir(cwd)
 165
 166         return v_output.ns
 167
 168     def do_finalize(self, fragment):
 169         super().do_finalize(fragment)
 170         return
 171         self.add_period_constraint(self.lookup_request("clk", loose=True),
 172                                    1e9/50e6)