6 from migen
import (Signal
, FSM
, If
, Display
, Finish
, NextValue
, NextState
)
8 from litex
.build
.generic_platform
import Pins
, Subsignal
9 from litex
.build
.sim
import SimPlatform
10 from litex
.build
.io
import CRG
11 from litex
.build
.sim
.config
import SimConfig
13 from litex
.soc
.integration
.soc
import SoCRegion
14 from litex
.soc
.integration
.soc_core
import SoCCore
15 from litex
.soc
.integration
.soc_sdram
import SoCSDRAM
16 from litex
.soc
.integration
.builder
import Builder
17 from litex
.soc
.integration
.common
import get_mem_data
19 from litedram
import modules
as litedram_modules
20 from litedram
.phy
.model
import SDRAMPHYModel
21 from litedram
.phy
.gensdrphy
import GENSDRPHY
, HalfRateGENSDRPHY
23 from litex
.soc
.cores
.gpio
import GPIOInOut
, GPIOIn
, GPIOOut
#, GPIOTristate
24 from litex
.soc
.cores
.spi
import SPIMaster
26 from litex
.tools
.litex_sim
import sdram_module_nphases
, get_sdram_phy_settings
28 from litex
.tools
.litex_sim
import Platform
29 from libresoc
.ls180
import LS180Platform
31 from migen
import Module
32 from litex
.soc
.interconnect
.csr
import AutoCSR
34 from libresoc
import LibreSoC
35 from microwatt
import Microwatt
38 from litex
.soc
.integration
.soc
import SoCCSRHandler
39 SoCCSRHandler
.supported_address_width
.append(12)
42 # LibreSoCSim -----------------------------------------------------------------
44 class LibreSoCSim(SoCCore
):
45 def __init__(self
, cpu
="libresoc", debug
=False, with_sdram
=True,
46 sdram_module
= "AS4C16M16",
47 #sdram_data_width = 16,
48 #sdram_module = "MT48LC16M16",
49 sdram_data_width
= 16,
50 irq_reserved_irqs
= {'uart': 0},
53 assert cpu
in ["libresoc", "microwatt"]
54 sys_clk_freq
= int(50e6
)
59 elif platform
== 'ls180':
60 platform
= LS180Platform()
68 # reserve XICS ICP and XICS memory addresses.
69 self
.mem_map
['icp'] = 0xc0010000
70 self
.mem_map
['ics'] = 0xc0011000
71 #self.csr_map["icp"] = 8 # 8 x 0x800 == 0x4000
72 #self.csr_map["ics"] = 10 # 10 x 0x800 == 0x5000
76 #ram_init = get_mem_data({
77 # ram_fname: "0x00000000",
79 ram_init
= get_mem_data(ram_fname
, "little")
81 # remap the main RAM to reset-start-address
83 # without sram nothing works, therefore move it to higher up
84 self
.mem_map
["sram"] = 0x90000000
86 # put UART at 0xc000200 (w00t! this works!)
87 self
.csr_map
["uart"] = 4
89 self
.mem_map
["main_ram"] = 0x90000000
90 self
.mem_map
["sram"] = 0x00000000
92 # SoCCore -------------------------------------------------------------
93 SoCCore
.__init
__(self
, platform
, clk_freq
=sys_clk_freq
,
94 cpu_type
= "microwatt",
95 cpu_cls
= LibreSoC
if cpu
== "libresoc" \
98 csr_address_width
= 14, # limit to 0x8000
99 cpu_variant
= variant
,
102 uart_name
= uart_name
,
103 with_sdram
= with_sdram
,
104 sdram_module
= sdram_module
,
105 sdram_data_width
= sdram_data_width
,
106 integrated_rom_size
= 0, # if ram_fname else 0x10000,
107 integrated_sram_size
= 0x200,
108 #integrated_main_ram_init = ram_init,
109 integrated_main_ram_size
= 0x00000000 if with_sdram \
110 else 0x10000000 , # 256MB
112 self
.platform
.name
= "ls180"
114 # SDR SDRAM ----------------------------------------------
115 if False: # not self.integrated_main_ram_size:
116 self
.submodules
.sdrphy
= sdrphy_cls(platform
.request("sdram"))
119 if cpu
== "libresoc":
120 # XICS interrupt devices
121 icp_addr
= self
.mem_map
['icp']
122 icp_wb
= self
.cpu
.xics_icp
123 icp_region
= SoCRegion(origin
=icp_addr
, size
=0x20, cached
=False)
124 self
.bus
.add_slave(name
='icp', slave
=icp_wb
, region
=icp_region
)
126 ics_addr
= self
.mem_map
['ics']
127 ics_wb
= self
.cpu
.xics_ics
128 ics_region
= SoCRegion(origin
=ics_addr
, size
=0x1000, cached
=False)
129 self
.bus
.add_slave(name
='ics', slave
=ics_wb
, region
=ics_region
)
131 # CRG -----------------------------------------------------------------
132 self
.submodules
.crg
= CRG(platform
.request("sys_clk"))
136 # SDRAM ----------------------------------------------------
138 sdram_clk_freq
= int(100e6
) # FIXME: use 100MHz timings
139 sdram_module_cls
= getattr(litedram_modules
, sdram_module
)
140 sdram_rate
= "1:{}".format(
141 sdram_module_nphases
[sdram_module_cls
.memtype
])
142 sdram_module
= sdram_module_cls(sdram_clk_freq
, sdram_rate
)
143 phy_settings
= get_sdram_phy_settings(
144 memtype
= sdram_module
.memtype
,
145 data_width
= sdram_data_width
,
146 clk_freq
= sdram_clk_freq
)
147 #sdrphy_cls = HalfRateGENSDRPHY
148 sdrphy_cls
= GENSDRPHY
149 self
.submodules
.sdrphy
= sdrphy_cls(platform
.request("sdram"))
150 #self.submodules.sdrphy = sdrphy_cls(sdram_module,
154 self
.add_sdram("sdram",
156 module
= sdram_module
,
157 origin
= self
.mem_map
["main_ram"],
159 l2_cache_size
= 0, # 8192
160 l2_cache_min_data_width
= 128,
161 l2_cache_reverse
= True
163 # FIXME: skip memtest to avoid corrupting memory
164 self
.add_constant("MEMTEST_BUS_SIZE", 128//16)
165 self
.add_constant("MEMTEST_DATA_SIZE", 128//16)
166 self
.add_constant("MEMTEST_ADDR_SIZE", 128//16)
167 self
.add_constant("MEMTEST_BUS_DEBUG", 1)
168 self
.add_constant("MEMTEST_ADDR_DEBUG", 1)
169 self
.add_constant("MEMTEST_DATA_DEBUG", 1)
172 #platform.add_extension([("gpio_in", 0, Pins(8))])
173 self
.submodules
.gpio_in
= GPIOIn(platform
.request("gpio_in"))
174 self
.add_csr("gpio_in")
175 self
.submodules
.gpio_out
= GPIOIn(platform
.request("gpio_out"))
176 self
.add_csr("gpio_out")
179 self
.submodules
.gpio
= GPIOTristate(platform
.request("gpio"))
183 self
.submodules
.spi_master
= SPIMaster(
184 pads
= platform
.request("spi_master"),
186 sys_clk_freq
= sys_clk_freq
,
189 self
.add_csr("spi_master")
191 # EINTs - very simple, wire up top 3 bits to ls180 "eint" pins
192 self
.comb
+= self
.cpu
.interrupt
[12:16].eq(platform
.request("eint"))
194 # Debug ---------------------------------------------------------------
198 # setup running of DMI FSM
201 dmi_dout
= Signal(64)
207 dbg_dout
= Signal(64)
210 # capture pc from dmi
212 active_dbg
= Signal()
213 active_dbg_cr
= Signal()
214 active_dbg_xer
= Signal()
223 # increment counter, Stop after 100000 cycles
225 self
.sync
+= uptime
.eq(uptime
+ 1)
226 #self.sync += If(uptime == 1000000000000, Finish())
228 # DMI FSM counter and FSM itself
229 dmicount
= Signal(10)
230 dmirunning
= Signal(1)
231 dmi_monitor
= Signal(1)
233 self
.submodules
+= dmifsm
237 If(dmi_req
& dmi_wen
,
238 (self
.cpu
.dmi_addr
.eq(dmi_addr
), # DMI Addr
239 self
.cpu
.dmi_din
.eq(dmi_din
), # DMI in
240 self
.cpu
.dmi_req
.eq(1), # DMI request
241 self
.cpu
.dmi_wr
.eq(1), # DMI write
248 If(dmi_req
& ~dmi_wen
,
249 (self
.cpu
.dmi_addr
.eq(dmi_addr
), # DMI Addr
250 self
.cpu
.dmi_req
.eq(1), # DMI request
251 self
.cpu
.dmi_wr
.eq(0), # DMI read
253 # acknowledge received: capture data.
255 NextValue(dbg_addr
, dmi_addr
),
256 NextValue(dbg_dout
, self
.cpu
.dmi_dout
),
257 NextValue(dbg_msg
, 1),
264 # DMI response received: reset the dmi request and check if
268 NextState("FIRE_MONITOR"), # fire "monitor" on next cycle
270 NextState("START"), # back to start on next cycle
272 NextValue(dmi_req
, 0),
273 NextValue(dmi_addr
, 0),
274 NextValue(dmi_din
, 0),
275 NextValue(dmi_wen
, 0),
278 # "monitor" mode fires off a STAT request
279 dmifsm
.act("FIRE_MONITOR",
280 (NextValue(dmi_req
, 1),
281 NextValue(dmi_addr
, 1), # DMI STAT address
282 NextValue(dmi_din
, 0),
283 NextValue(dmi_wen
, 0), # read STAT
284 NextState("START"), # back to start on next cycle
288 self
.comb
+= xer_so
.eq((dbg_dout
& 1) == 1)
289 self
.comb
+= xer_ca
.eq((dbg_dout
& 4) == 4)
290 self
.comb
+= xer_ca32
.eq((dbg_dout
& 8) == 8)
291 self
.comb
+= xer_ov
.eq((dbg_dout
& 16) == 16)
292 self
.comb
+= xer_ov32
.eq((dbg_dout
& 32) == 32)
295 self
.sync
+= If(dbg_msg
,
296 (If(active_dbg
& (dbg_addr
== 0b10), # PC
297 Display("pc : %016x", dbg_dout
),
299 If(dbg_addr
== 0b10, # PC
300 pc
.eq(dbg_dout
), # capture PC
302 #If(dbg_addr == 0b11, # MSR
303 # Display(" msr: %016x", dbg_dout),
305 If(dbg_addr
== 0b1000, # CR
306 Display(" cr : %016x", dbg_dout
),
308 If(dbg_addr
== 0b1001, # XER
309 Display(" xer: so %d ca %d 32 %d ov %d 32 %d",
310 xer_so
, xer_ca
, xer_ca32
, xer_ov
, xer_ov32
),
312 If(dbg_addr
== 0b101, # GPR
313 Display(" gpr: %016x", dbg_dout
),
315 # also check if this is a "stat"
316 If(dbg_addr
== 1, # requested a STAT
317 #Display(" stat: %x", dbg_dout),
318 If(dbg_dout
& 2, # bit 2 of STAT is "stopped" mode
319 dmirunning
.eq(1), # continue running
320 dmi_monitor
.eq(0), # and stop monitor mode
328 self
.sync
+= If(uptime
== 0,
329 (dmi_addr
.eq(0), # CTRL
330 dmi_din
.eq(1<<0), # STOP
336 self
.sync
+= If(uptime
== 4,
340 self
.sync
+= If(dmirunning
,
341 dmicount
.eq(dmicount
+ 1),
344 # loop every 1<<N cycles
348 self
.sync
+= If(dmicount
== 4,
349 (dmi_addr
.eq(0b10), # NIA
356 self
.sync
+= If(dmicount
== 8,
357 (dmi_addr
.eq(0), # CTRL
358 dmi_din
.eq(1<<3), # STEP
361 dmirunning
.eq(0), # stop counter, need to fire "monitor"
362 dmi_monitor
.eq(1), # start "monitor" instead
366 # limit range of pc for debug reporting
367 #self.comb += active_dbg.eq((0x378c <= pc) & (pc <= 0x38d8))
368 #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58))
369 self
.comb
+= active_dbg
.eq(1)
373 self
.sync
+= If(active_dbg
& (dmicount
== 12),
374 (dmi_addr
.eq(0b11), # MSR
380 if cpu
== "libresoc":
381 #self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12600))
382 self
.comb
+= active_dbg_cr
.eq(0)
385 self
.sync
+= If(active_dbg_cr
& (dmicount
== 16),
386 (dmi_addr
.eq(0b1000), # CR
392 #self.comb += active_dbg_xer.eq((0x10300 <= pc) & (pc <= 0x1094c))
393 self
.comb
+= active_dbg_xer
.eq(active_dbg_cr
)
396 self
.sync
+= If(active_dbg_xer
& (dmicount
== 20),
397 (dmi_addr
.eq(0b1001), # XER
405 self
.sync
+= If(active_dbg
& (dmicount
== 24+(i
*8)),
406 (dmi_addr
.eq(0b100), # GSPR addr
413 self
.sync
+= If(active_dbg
& (dmicount
== 28+(i
*8)),
414 (dmi_addr
.eq(0b101), # GSPR data
420 # monitor bbus read/write
421 self
.sync
+= If(active_dbg
& self
.cpu
.dbus
.stb
& self
.cpu
.dbus
.ack
,
422 Display(" [%06x] dadr: %8x, we %d s %01x w %016x r: %016x",
436 self
.sync
+= If(active_dbg
& self
.cpu
.ibus
.stb
& self
.cpu
.ibus
.ack
&
438 Display(" [%06x] iadr: %8x, s %01x w %016x",
447 self
.sync
+= If(active_dbg
& self
.cpu
.ibus
.stb
& self
.cpu
.ibus
.ack
&
449 Display(" [%06x] iadr: %8x, s %01x r %016x",
458 # Build -----------------------------------------------------------------------
461 parser
= argparse
.ArgumentParser(description
="LiteX LibreSoC CPU Sim")
462 parser
.add_argument("--cpu", default
="libresoc",
463 help="CPU to use: libresoc (default) or microwatt")
464 parser
.add_argument("--platform", default
="sim",
465 help="platform (sim or ls180)")
466 parser
.add_argument("--debug", action
="store_true",
467 help="Enable debug traces")
468 parser
.add_argument("--trace", action
="store_true",
469 help="Enable tracing")
470 parser
.add_argument("--trace-start", default
=0,
471 help="Cycle to start FST tracing")
472 parser
.add_argument("--trace-end", default
=-1,
473 help="Cycle to end FST tracing")
474 parser
.add_argument("--build", action
="store_true", help="Build bitstream")
475 args
= parser
.parse_args()
478 if args
.platform
== 'ls180':
479 soc
= LibreSoCSim(cpu
=args
.cpu
, debug
=args
.debug
,
480 platform
=args
.platform
)
483 builder
= Builder(soc
, compile_gateware
= True)
484 builder
.build(run
= True)
488 sim_config
= SimConfig(default_clk
="sys_clk")
489 sim_config
.add_module("serial2console", "serial")
492 soc
= LibreSoCSim(cpu
=args
.cpu
, debug
=args
.debug
,
493 platform
=args
.platform
)
494 builder
= Builder(soc
, compile_gateware
= i
!=0)
495 builder
.build(sim_config
=sim_config
,
498 trace_start
= int(args
.trace_start
),
499 trace_end
= int(args
.trace_end
),
503 if __name__
== "__main__":