src/soc/litex/florent/sim.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 import argparse
   5
   6 from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState)
   7
   8 from litex.build.generic_platform import Pins, Subsignal
   9 from litex.build.sim import SimPlatform
  10 from litex.build.io import CRG
  11 from litex.build.sim.config import SimConfig
  12
  13 from litex.soc.integration.soc import SoCRegion
  14 from litex.soc.integration.soc_core import SoCCore
  15 from litex.soc.integration.soc_sdram import SoCSDRAM
  16 from litex.soc.integration.builder import Builder
  17 from litex.soc.integration.common import get_mem_data
  18
  19 from litedram import modules as litedram_modules
  20 from litedram.phy.model import SDRAMPHYModel
  21 from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings
  22
  23 from litex.tools.litex_sim import Platform
  24
  25 from libresoc import LibreSoC
  26 from microwatt import Microwatt
  27
  28 # HACK!
  29 from litex.soc.integration.soc import SoCCSRHandler
  30 SoCCSRHandler.supported_address_width.append(12)
  31
  32 # LibreSoCSim -----------------------------------------------------------------
  33
  34 class LibreSoCSim(SoCSDRAM):
  35     def __init__(self, cpu="libresoc", debug=False, with_sdram=True,
  36             sdram_module          = "AS4C16M16",
  37             #sdram_data_width      = 16,
  38             #sdram_module          = "MT48LC16M16",
  39             sdram_data_width      = 16,
  40             irq_reserved_irqs = {'uart': 0},
  41             ):
  42         assert cpu in ["libresoc", "microwatt"]
  43         platform     = Platform()
  44         sys_clk_freq = int(100e6)
  45
  46         #cpu_data_width = 32
  47         cpu_data_width = 64
  48
  49         if cpu_data_width == 32:
  50             variant = "standard32"
  51         else:
  52             variant = "standard"
  53
  54         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
  55         #            "hello_world/hello_world.bin"
  56         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
  57                     "tests/1.bin"
  58         #ram_fname = "/tmp/test.bin"
  59         #ram_fname = None
  60         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
  61         #            "micropython/firmware.bin"
  62         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
  63         #            "tests/xics/xics.bin"
  64         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
  65         #            "tests/decrementer/decrementer.bin"
  66         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
  67         #            "hello_world/hello_world.bin"
  68
  69         # reserve XICS ICP and XICS memory addresses.
  70         self.mem_map['icp'] = 0xc0004000
  71         self.mem_map['ics'] = 0xc0005000
  72         self.mem_map['gpio'] = 0xc0007000
  73         #self.csr_map["icp"] = 8  #  8 x 0x800 == 0x4000
  74         #self.csr_map["ics"] = 10 # 10 x 0x800 == 0x5000
  75
  76         ram_init = []
  77         if ram_fname:
  78             #ram_init = get_mem_data({
  79             #    ram_fname:       "0x00000000",
  80             #    }, "little")
  81             ram_init = get_mem_data(ram_fname, "little")
  82
  83             # remap the main RAM to reset-start-address
  84             self.mem_map["main_ram"] = 0x00000000
  85
  86             # without sram nothing works, therefore move it to higher up
  87             self.mem_map["sram"] = 0x90000000
  88
  89             # put UART at 0xc000200 (w00t!  this works!)
  90             self.csr_map["uart"] = 4
  91
  92
  93         # SoCCore -------------------------------------------------------------
  94         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
  95             cpu_type                 = "microwatt",
  96             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
  97                                        else Microwatt,
  98             #bus_data_width           = 64,
  99             csr_address_width        = 12, # limit to 0x4000
 100             cpu_variant              = variant,
 101             csr_data_width            = 8,
 102             l2_size             = 0,
 103             uart_name                = "sim",
 104             with_sdram               = with_sdram,
 105             sdram_module          = sdram_module,
 106             sdram_data_width      = sdram_data_width,
 107             integrated_rom_size      = 0 if ram_fname else 0x10000,
 108             integrated_sram_size     = 0x40000,
 109             #integrated_main_ram_init  = ram_init,
 110             integrated_main_ram_size = 0x00000000 if with_sdram \
 111                                         else 0x10000000 , # 256MB
 112             )
 113         self.platform.name = "sim"
 114
 115         if cpu == "libresoc":
 116             # XICS interrupt devices
 117             icp_addr = self.mem_map['icp']
 118             icp_wb = self.cpu.xics_icp
 119             icp_region = SoCRegion(origin=icp_addr, size=0x20, cached=False)
 120             self.bus.add_slave(name='icp', slave=icp_wb, region=icp_region)
 121
 122             ics_addr = self.mem_map['ics']
 123             ics_wb = self.cpu.xics_ics
 124             ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
 125             self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
 126
 127             # Simple GPIO peripheral
 128             gpio_addr = self.mem_map['gpio']
 129             gpio_wb = self.cpu.simple_gpio
 130             gpio_region = SoCRegion(origin=gpio_addr, size=0x20, cached=False)
 131             self.bus.add_slave(name='gpio', slave=gpio_wb, region=gpio_region)
 132
 133
 134         # CRG -----------------------------------------------------------------
 135         self.submodules.crg = CRG(platform.request("sys_clk"))
 136
 137         #ram_init = []
 138
 139         # SDRAM ----------------------------------------------------
 140         if with_sdram:
 141             sdram_clk_freq   = int(100e6) # FIXME: use 100MHz timings
 142             sdram_module_cls = getattr(litedram_modules, sdram_module)
 143             sdram_rate       = "1:{}".format(
 144                     sdram_module_nphases[sdram_module_cls.memtype])
 145             sdram_module     = sdram_module_cls(sdram_clk_freq, sdram_rate)
 146             phy_settings     = get_sdram_phy_settings(
 147                             memtype    = sdram_module.memtype,
 148                             data_width = sdram_data_width,
 149                             clk_freq   = sdram_clk_freq)
 150             self.submodules.sdrphy = SDRAMPHYModel(sdram_module,
 151                                                    phy_settings,
 152                                                    init=ram_init
 153                                                     )
 154             self.register_sdram(
 155                             self.sdrphy,
 156                             sdram_module.geom_settings,
 157                             sdram_module.timing_settings)
 158             # FIXME: skip memtest to avoid corrupting memory
 159             self.add_constant("MEMTEST_BUS_SIZE",  128//16)
 160             self.add_constant("MEMTEST_DATA_SIZE", 128//16)
 161             self.add_constant("MEMTEST_ADDR_SIZE", 128//16)
 162             self.add_constant("MEMTEST_BUS_DEBUG", 1)
 163             self.add_constant("MEMTEST_ADDR_DEBUG", 1)
 164             self.add_constant("MEMTEST_DATA_DEBUG", 1)
 165
 166
 167         # Debug ---------------------------------------------------------------
 168         if not debug:
 169             return
 170
 171         # setup running of DMI FSM
 172         dmi_addr = Signal(4)
 173         dmi_din = Signal(64)
 174         dmi_dout = Signal(64)
 175         dmi_wen = Signal(1)
 176         dmi_req = Signal(1)
 177
 178         # debug log out
 179         dbg_addr = Signal(4)
 180         dbg_dout = Signal(64)
 181         dbg_msg = Signal(1)
 182
 183         # capture pc from dmi
 184         pc = Signal(64)
 185         active_dbg = Signal()
 186         active_dbg_cr = Signal()
 187         active_dbg_xer = Signal()
 188
 189         # xer flags
 190         xer_so = Signal()
 191         xer_ca = Signal()
 192         xer_ca32 = Signal()
 193         xer_ov = Signal()
 194         xer_ov32 = Signal()
 195
 196         # increment counter, Stop after 100000 cycles
 197         uptime = Signal(64)
 198         self.sync += uptime.eq(uptime + 1)
 199         #self.sync += If(uptime == 1000000000000, Finish())
 200
 201         # DMI FSM counter and FSM itself
 202         dmicount = Signal(10)
 203         dmirunning = Signal(1)
 204         dmi_monitor = Signal(1)
 205         dmifsm = FSM()
 206         self.submodules += dmifsm
 207
 208         # DMI FSM
 209         dmifsm.act("START",
 210             If(dmi_req & dmi_wen,
 211                 (self.cpu.dmi_addr.eq(dmi_addr),   # DMI Addr
 212                  self.cpu.dmi_din.eq(dmi_din), # DMI in
 213                  self.cpu.dmi_req.eq(1),    # DMI request
 214                  self.cpu.dmi_wr.eq(1),    # DMI write
 215                  If(self.cpu.dmi_ack,
 216                     (NextState("IDLE"),
 217                     )
 218                  ),
 219                 ),
 220             ),
 221             If(dmi_req & ~dmi_wen,
 222                 (self.cpu.dmi_addr.eq(dmi_addr),   # DMI Addr
 223                  self.cpu.dmi_req.eq(1),    # DMI request
 224                  self.cpu.dmi_wr.eq(0),    # DMI read
 225                  If(self.cpu.dmi_ack,
 226                     # acknowledge received: capture data.
 227                     (NextState("IDLE"),
 228                      NextValue(dbg_addr, dmi_addr),
 229                      NextValue(dbg_dout, self.cpu.dmi_dout),
 230                      NextValue(dbg_msg, 1),
 231                     ),
 232                  ),
 233                 ),
 234             )
 235         )
 236
 237         # DMI response received: reset the dmi request and check if
 238         # in "monitor" mode
 239         dmifsm.act("IDLE",
 240             If(dmi_monitor,
 241                  NextState("FIRE_MONITOR"), # fire "monitor" on next cycle
 242             ).Else(
 243                  NextState("START"), # back to start on next cycle
 244             ),
 245             NextValue(dmi_req, 0),
 246             NextValue(dmi_addr, 0),
 247             NextValue(dmi_din, 0),
 248             NextValue(dmi_wen, 0),
 249         )
 250
 251         # "monitor" mode fires off a STAT request
 252         dmifsm.act("FIRE_MONITOR",
 253             (NextValue(dmi_req, 1),
 254              NextValue(dmi_addr, 1), # DMI STAT address
 255              NextValue(dmi_din, 0),
 256              NextValue(dmi_wen, 0), # read STAT
 257              NextState("START"), # back to start on next cycle
 258             )
 259         )
 260
 261         self.comb += xer_so.eq((dbg_dout & 1) == 1)
 262         self.comb += xer_ca.eq((dbg_dout & 4) == 4)
 263         self.comb += xer_ca32.eq((dbg_dout & 8) == 8)
 264         self.comb += xer_ov.eq((dbg_dout & 16) == 16)
 265         self.comb += xer_ov32.eq((dbg_dout & 32) == 32)
 266
 267         # debug messages out
 268         self.sync += If(dbg_msg,
 269             (If(active_dbg & (dbg_addr == 0b10), # PC
 270                 Display("pc : %016x", dbg_dout),
 271              ),
 272              If(dbg_addr == 0b10, # PC
 273                  pc.eq(dbg_dout),     # capture PC
 274              ),
 275              #If(dbg_addr == 0b11, # MSR
 276              #   Display("    msr: %016x", dbg_dout),
 277              #),
 278              If(dbg_addr == 0b1000, # CR
 279                 Display("    cr : %016x", dbg_dout),
 280              ),
 281              If(dbg_addr == 0b1001, # XER
 282                 Display("    xer: so %d ca %d 32 %d ov %d 32 %d",
 283                             xer_so, xer_ca, xer_ca32, xer_ov, xer_ov32),
 284              ),
 285              If(dbg_addr == 0b101, # GPR
 286                 Display("    gpr: %016x", dbg_dout),
 287              ),
 288             # also check if this is a "stat"
 289             If(dbg_addr == 1, # requested a STAT
 290                 #Display("    stat: %x", dbg_dout),
 291                 If(dbg_dout & 2, # bit 2 of STAT is "stopped" mode
 292                      dmirunning.eq(1), # continue running
 293                      dmi_monitor.eq(0), # and stop monitor mode
 294                 ),
 295             ),
 296              dbg_msg.eq(0)
 297             )
 298         )
 299
 300         # kick off a "stop"
 301         self.sync += If(uptime == 0,
 302             (dmi_addr.eq(0), # CTRL
 303              dmi_din.eq(1<<0), # STOP
 304              dmi_req.eq(1),
 305              dmi_wen.eq(1),
 306             )
 307         )
 308
 309         self.sync += If(uptime == 4,
 310              dmirunning.eq(1),
 311         )
 312
 313         self.sync += If(dmirunning,
 314              dmicount.eq(dmicount + 1),
 315         )
 316
 317         # loop every 1<<N cycles
 318         cyclewid = 9
 319
 320         # get the PC
 321         self.sync += If(dmicount == 4,
 322             (dmi_addr.eq(0b10), # NIA
 323              dmi_req.eq(1),
 324              dmi_wen.eq(0),
 325             )
 326         )
 327
 328         # kick off a "step"
 329         self.sync += If(dmicount == 8,
 330             (dmi_addr.eq(0), # CTRL
 331              dmi_din.eq(1<<3), # STEP
 332              dmi_req.eq(1),
 333              dmi_wen.eq(1),
 334              dmirunning.eq(0), # stop counter, need to fire "monitor"
 335              dmi_monitor.eq(1), # start "monitor" instead
 336             )
 337         )
 338
 339         # limit range of pc for debug reporting
 340         #self.comb += active_dbg.eq((0x378c <= pc) & (pc <= 0x38d8))
 341         #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58))
 342         self.comb += active_dbg.eq(1)
 343
 344
 345         # get the MSR
 346         self.sync += If(active_dbg & (dmicount == 12),
 347             (dmi_addr.eq(0b11), # MSR
 348              dmi_req.eq(1),
 349              dmi_wen.eq(0),
 350             )
 351         )
 352
 353         if cpu == "libresoc":
 354             #self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12600))
 355             self.comb += active_dbg_cr.eq(0)
 356
 357             # get the CR
 358             self.sync += If(active_dbg_cr & (dmicount == 16),
 359                 (dmi_addr.eq(0b1000), # CR
 360                  dmi_req.eq(1),
 361                  dmi_wen.eq(0),
 362                 )
 363             )
 364
 365             #self.comb += active_dbg_xer.eq((0x10300 <= pc) & (pc <= 0x1094c))
 366             self.comb += active_dbg_xer.eq(active_dbg_cr)
 367
 368             # get the CR
 369             self.sync += If(active_dbg_xer & (dmicount == 20),
 370                 (dmi_addr.eq(0b1001), # XER
 371                  dmi_req.eq(1),
 372                  dmi_wen.eq(0),
 373                 )
 374             )
 375
 376         # read all 32 GPRs
 377         for i in range(32):
 378             self.sync += If(active_dbg & (dmicount == 24+(i*8)),
 379                 (dmi_addr.eq(0b100), # GSPR addr
 380                  dmi_din.eq(i), # r1
 381                  dmi_req.eq(1),
 382                  dmi_wen.eq(1),
 383                 )
 384             )
 385
 386             self.sync += If(active_dbg & (dmicount == 28+(i*8)),
 387                 (dmi_addr.eq(0b101), # GSPR data
 388                  dmi_req.eq(1),
 389                  dmi_wen.eq(0),
 390                 )
 391             )
 392
 393         # monitor bbus read/write
 394         self.sync += If(active_dbg & self.cpu.dbus.stb & self.cpu.dbus.ack,
 395             Display("    [%06x] dadr: %8x, we %d s %01x w %016x r: %016x",
 396                 #uptime,
 397                 0,
 398                 self.cpu.dbus.adr,
 399                 self.cpu.dbus.we,
 400                 self.cpu.dbus.sel,
 401                 self.cpu.dbus.dat_w,
 402                 self.cpu.dbus.dat_r
 403             )
 404         )
 405
 406         return
 407
 408         # monitor ibus write
 409         self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
 410                         self.cpu.ibus.we,
 411             Display("    [%06x] iadr: %8x, s %01x w %016x",
 412                 #uptime,
 413                 0,
 414                 self.cpu.ibus.adr,
 415                 self.cpu.ibus.sel,
 416                 self.cpu.ibus.dat_w,
 417             )
 418         )
 419         # monitor ibus read
 420         self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
 421                         ~self.cpu.ibus.we,
 422             Display("    [%06x] iadr: %8x, s %01x r %016x",
 423                 #uptime,
 424                 0,
 425                 self.cpu.ibus.adr,
 426                 self.cpu.ibus.sel,
 427                 self.cpu.ibus.dat_r
 428             )
 429         )
 430
 431 # Build -----------------------------------------------------------------------
 432
 433 def main():
 434     parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
 435     parser.add_argument("--cpu",          default="libresoc",
 436                         help="CPU to use: libresoc (default) or microwatt")
 437     parser.add_argument("--debug",        action="store_true",
 438                         help="Enable debug traces")
 439     parser.add_argument("--trace",        action="store_true",
 440                         help="Enable tracing")
 441     parser.add_argument("--trace-start",  default=0,
 442                         help="Cycle to start FST tracing")
 443     parser.add_argument("--trace-end",    default=-1,
 444                         help="Cycle to end FST tracing")
 445     args = parser.parse_args()
 446
 447     sim_config = SimConfig(default_clk="sys_clk")
 448     sim_config.add_module("serial2console", "serial")
 449
 450     for i in range(2):
 451         soc = LibreSoCSim(cpu=args.cpu, debug=args.debug)
 452         builder = Builder(soc,compile_gateware = i!=0)
 453         builder.build(sim_config=sim_config,
 454             run         = i!=0,
 455             trace       = args.trace,
 456             trace_start = int(args.trace_start),
 457             trace_end   = int(args.trace_end),
 458             trace_fst   = 0)
 459         os.chdir("../")
 460
 461 if __name__ == "__main__":
 462     main()