src/soc/litex/florent/sim.py

   1 #!/usr/bin/env python3
   2
   3 import argparse
   4
   5 from migen import *
   6
   7 from litex.build.generic_platform import *
   8 from litex.build.sim import SimPlatform
   9 from litex.build.sim.config import SimConfig
  10
  11 from litex.soc.integration.soc_core import *
  12 from litex.soc.integration.builder import *
  13
  14 from litex.tools.litex_sim import Platform
  15
  16 from libresoc import LibreSoC
  17 from microwatt import Microwatt
  18
  19 # LibreSoCSim --------------------------------------------------------------------------------------
  20
  21 class LibreSoCSim(SoCCore):
  22     def __init__(self, cpu="libresoc", debug=False):
  23         assert cpu in ["libresoc", "microwatt"]
  24         platform     = Platform()
  25         sys_clk_freq = int(1e6)
  26
  27         # SoCCore ----------------------------------------------------------------------------------
  28         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
  29             cpu_type                 = "microwatt",
  30             cpu_cls                  = LibreSoC   if cpu == "libresoc" else Microwatt,
  31             uart_name                = "sim",
  32             integrated_rom_size      = 0x10000,
  33             integrated_main_ram_size = 0x10000000) # 256MB
  34         self.platform.name = "sim"
  35
  36         # CRG --------------------------------------------------------------------------------------
  37         self.submodules.crg = CRG(platform.request("sys_clk"))
  38
  39         # Debug ------------------------------------------------------------------------------------
  40         if debug:
  41             uptime = Signal(64)
  42             self.sync += uptime.eq(uptime + 1)
  43             self.sync += If(self.cpu.ibus.stb & self.cpu.ibus.ack &
  44                             self.cpu.ibus.we,
  45                 Display("[%06x] iadr: %8x, s %01x w %016x",
  46                     uptime,
  47                     self.cpu.ibus.adr,
  48                     self.cpu.ibus.sel,
  49                     self.cpu.ibus.dat_w,
  50                 )
  51             )
  52             self.sync += If(self.cpu.ibus.stb & self.cpu.ibus.ack &
  53                             ~self.cpu.ibus.we,
  54                 Display("[%06x] iadr: %8x, s %01x r %016x",
  55                     uptime,
  56                     self.cpu.ibus.adr,
  57                     self.cpu.ibus.sel,
  58                     self.cpu.ibus.dat_r
  59                 )
  60             )
  61             self.sync += If(self.cpu.dbus.stb & self.cpu.dbus.ack,
  62                 Display("[%06x] dadr: %8x, we %d s %01x w %016x r: %016x",
  63                     uptime,
  64                     self.cpu.dbus.adr,
  65                     self.cpu.dbus.we,
  66                     self.cpu.dbus.sel,
  67                     self.cpu.dbus.dat_w,
  68                     self.cpu.dbus.dat_r
  69                 )
  70             )
  71             # Stop after 20000 cycles
  72             self.sync += If(uptime == 100000, Finish())
  73
  74 # Build --------------------------------------------------------------------------------------------
  75
  76 def main():
  77     parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Simulation")
  78     parser.add_argument("--cpu",          default="libresoc",  help="CPU to use: libresoc (default) or microwatt")
  79     parser.add_argument("--debug",        action="store_true", help="Enable debug traces")
  80     parser.add_argument("--trace",        action="store_true", help="Enable tracing")
  81     parser.add_argument("--trace-start",  default=0,           help="Cycle to start FST tracing")
  82     parser.add_argument("--trace-end",    default=-1,          help="Cycle to end FST tracing")
  83     args = parser.parse_args()
  84
  85     sim_config = SimConfig(default_clk="sys_clk")
  86     sim_config.add_module("serial2console", "serial")
  87
  88     for i in range(2):
  89         soc = LibreSoCSim(cpu=args.cpu, debug=args.debug)
  90         builder = Builder(soc,compile_gateware = i!=0)
  91         builder.build(sim_config=sim_config,
  92             run         = i!=0,
  93             trace       = args.trace,
  94             trace_start = int(args.trace_start),
  95             trace_end   = int(args.trace_end),
  96             trace_fst   = 0)
  97         os.chdir("../")
  98
  99 if __name__ == "__main__":
 100     main()