src/soc/litex/florent/sim.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 import argparse
   5
   6 from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState)
   7
   8 from litex.build.generic_platform import Pins, Subsignal
   9 from litex.build.sim import SimPlatform
  10 from litex.build.io import CRG
  11 from litex.build.sim.config import SimConfig
  12
  13 from litex.soc.integration.soc import SoCRegion
  14 from litex.soc.integration.soc_core import SoCCore
  15 from litex.soc.integration.soc_sdram import SoCSDRAM
  16 from litex.soc.integration.builder import Builder
  17 from litex.soc.integration.common import get_mem_data
  18
  19 from litedram import modules as litedram_modules
  20 from litedram.phy.model import SDRAMPHYModel
  21 from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings
  22
  23 from litex.tools.litex_sim import Platform
  24
  25 from libresoc import LibreSoC
  26 from microwatt import Microwatt
  27
  28 # LibreSoCSim -----------------------------------------------------------------
  29
  30 class LibreSoCSim(SoCSDRAM):
  31     def __init__(self, cpu="libresoc", debug=False, with_sdram=True,
  32             sdram_module          = "AS4C16M16",
  33             #sdram_data_width      = 16,
  34             #sdram_module          = "MT48LC16M16",
  35             sdram_data_width      = 16,
  36             ):
  37         assert cpu in ["libresoc", "microwatt"]
  38         platform     = Platform()
  39         sys_clk_freq = int(100e6)
  40
  41         #cpu_data_width = 32
  42         cpu_data_width = 64
  43
  44         if cpu_data_width == 32:
  45             variant = "standard32"
  46         else:
  47             variant = "standard"
  48
  49         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
  50         #            "hello_world/hello_world.bin"
  51         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
  52                     "tests/1.bin"
  53         #ram_fname = "/tmp/test.bin"
  54         #ram_fname = None
  55
  56         ram_init = []
  57         if ram_fname:
  58             #ram_init = get_mem_data({
  59             #    ram_fname:       "0x00000000",
  60             #    }, "little")
  61             ram_init = get_mem_data(ram_fname, "little")
  62
  63             # remap the main RAM to reset-start-address
  64             self.mem_map["main_ram"] = 0x00000000
  65
  66             # without sram nothing works, therefore move it to higher up
  67             self.mem_map["sram"] = 0x90000000
  68
  69
  70         # SoCCore -------------------------------------------------------------
  71         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
  72             cpu_type                 = "microwatt",
  73             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
  74                                        else Microwatt,
  75             #bus_data_width           = 64,
  76             cpu_variant              = variant,
  77             csr_data_width            = 32,
  78             l2_size             = 0,
  79             uart_name                = "sim",
  80             with_sdram               = with_sdram,
  81             sdram_module          = sdram_module,
  82             sdram_data_width      = sdram_data_width,
  83             integrated_rom_size      = 0 if ram_fname else 0x10000,
  84             integrated_sram_size     = 0x40000,
  85             #integrated_main_ram_init  = ram_init,
  86             integrated_main_ram_size = 0x00000000 if with_sdram \
  87                                         else 0x10000000 , # 256MB
  88             )
  89         self.platform.name = "sim"
  90
  91         # CRG -----------------------------------------------------------------
  92         self.submodules.crg = CRG(platform.request("sys_clk"))
  93
  94         #ram_init = []
  95
  96         # SDRAM ----------------------------------------------------
  97         if with_sdram:
  98             sdram_clk_freq   = int(100e6) # FIXME: use 100MHz timings
  99             sdram_module_cls = getattr(litedram_modules, sdram_module)
 100             sdram_rate       = "1:{}".format(
 101                     sdram_module_nphases[sdram_module_cls.memtype])
 102             sdram_module     = sdram_module_cls(sdram_clk_freq, sdram_rate)
 103             phy_settings     = get_sdram_phy_settings(
 104                             memtype    = sdram_module.memtype,
 105                             data_width = sdram_data_width,
 106                             clk_freq   = sdram_clk_freq)
 107             self.submodules.sdrphy = SDRAMPHYModel(sdram_module,
 108                                                    phy_settings,
 109                                                    init=ram_init
 110                                                     )
 111             self.register_sdram(
 112                             self.sdrphy,
 113                             sdram_module.geom_settings,
 114                             sdram_module.timing_settings)
 115             # FIXME: skip memtest to avoid corrupting memory
 116             self.add_constant("MEMTEST_BUS_SIZE",  128//16)
 117             self.add_constant("MEMTEST_DATA_SIZE", 128//16)
 118             self.add_constant("MEMTEST_ADDR_SIZE", 128//16)
 119             self.add_constant("MEMTEST_BUS_DEBUG", 1)
 120             self.add_constant("MEMTEST_ADDR_DEBUG", 1)
 121             self.add_constant("MEMTEST_DATA_DEBUG", 1)
 122
 123
 124         # Debug ---------------------------------------------------------------
 125         if not debug:
 126             return
 127
 128         # setup running of DMI FSM
 129         dmi_addr = Signal(4)
 130         dmi_din = Signal(64)
 131         dmi_dout = Signal(64)
 132         dmi_wen = Signal(1)
 133         dmi_req = Signal(1)
 134
 135         # debug log out
 136         dbg_addr = Signal(4)
 137         dbg_dout = Signal(64)
 138         dbg_msg = Signal(1)
 139
 140         # capture pc from dmi
 141         pc = Signal(64)
 142         active_dbg = Signal()
 143         active_dbg_cr = Signal()
 144
 145         # increment counter, Stop after 100000 cycles
 146         uptime = Signal(64)
 147         self.sync += uptime.eq(uptime + 1)
 148         #self.sync += If(uptime == 1000000000000, Finish())
 149
 150         # DMI FSM counter and FSM itself
 151         dmicount = Signal(10)
 152         dmirunning = Signal(1)
 153         dmi_monitor = Signal(1)
 154         dmifsm = FSM()
 155         self.submodules += dmifsm
 156
 157         # DMI FSM
 158         dmifsm.act("START",
 159             If(dmi_req & dmi_wen,
 160                 (self.cpu.dmi_addr.eq(dmi_addr),   # DMI Addr
 161                  self.cpu.dmi_din.eq(dmi_din), # DMI in
 162                  self.cpu.dmi_req.eq(1),    # DMI request
 163                  self.cpu.dmi_wr.eq(1),    # DMI write
 164                  If(self.cpu.dmi_ack,
 165                     (NextState("IDLE"),
 166                     )
 167                  ),
 168                 ),
 169             ),
 170             If(dmi_req & ~dmi_wen,
 171                 (self.cpu.dmi_addr.eq(dmi_addr),   # DMI Addr
 172                  self.cpu.dmi_req.eq(1),    # DMI request
 173                  self.cpu.dmi_wr.eq(0),    # DMI read
 174                  If(self.cpu.dmi_ack,
 175                     # acknowledge received: capture data.
 176                     (NextState("IDLE"),
 177                      NextValue(dbg_addr, dmi_addr),
 178                      NextValue(dbg_dout, self.cpu.dmi_dout),
 179                      NextValue(dbg_msg, 1),
 180                     ),
 181                  ),
 182                 ),
 183             )
 184         )
 185
 186         # DMI response received: reset the dmi request and check if
 187         # in "monitor" mode
 188         dmifsm.act("IDLE",
 189             If(dmi_monitor,
 190                  NextState("FIRE_MONITOR"), # fire "monitor" on next cycle
 191             ).Else(
 192                  NextState("START"), # back to start on next cycle
 193             ),
 194             NextValue(dmi_req, 0),
 195             NextValue(dmi_addr, 0),
 196             NextValue(dmi_din, 0),
 197             NextValue(dmi_wen, 0),
 198         )
 199
 200         # "monitor" mode fires off a STAT request
 201         dmifsm.act("FIRE_MONITOR",
 202             (NextValue(dmi_req, 1),
 203              NextValue(dmi_addr, 1), # DMI STAT address
 204              NextValue(dmi_din, 0),
 205              NextValue(dmi_wen, 0), # read STAT
 206              NextState("START"), # back to start on next cycle
 207             )
 208         )
 209
 210         # debug messages out
 211         self.sync += If(dbg_msg,
 212             (If(active_dbg & (dbg_addr == 0b10), # PC
 213                 Display("pc : %016x", dbg_dout),
 214              ),
 215              If(dbg_addr == 0b10, # PC
 216                  pc.eq(dbg_dout),     # capture PC
 217              ),
 218              #If(dbg_addr == 0b11, # MSR
 219              #   Display("    msr: %016x", dbg_dout),
 220              #),
 221              If(dbg_addr == 0b1000, # CR
 222                 Display("    cr: %016x", dbg_dout),
 223              ),
 224              If(dbg_addr == 0b101, # GPR
 225                 Display("    gpr: %016x", dbg_dout),
 226              ),
 227             # also check if this is a "stat"
 228             If(dbg_addr == 1, # requested a STAT
 229                 #Display("    stat: %x", dbg_dout),
 230                 If(dbg_dout & 2, # bit 2 of STAT is "stopped" mode
 231                      dmirunning.eq(1), # continue running
 232                      dmi_monitor.eq(0), # and stop monitor mode
 233                 ),
 234             ),
 235              dbg_msg.eq(0)
 236             )
 237         )
 238
 239         # kick off a "stop"
 240         self.sync += If(uptime == 0,
 241             (dmi_addr.eq(0), # CTRL
 242              dmi_din.eq(1<<0), # STOP
 243              dmi_req.eq(1),
 244              dmi_wen.eq(1),
 245             )
 246         )
 247
 248         self.sync += If(uptime == 4,
 249              dmirunning.eq(1),
 250         )
 251
 252         self.sync += If(dmirunning,
 253              dmicount.eq(dmicount + 1),
 254         )
 255
 256         # loop every 1<<N cycles
 257         cyclewid = 9
 258
 259         # get the PC
 260         self.sync += If(dmicount == 4,
 261             (dmi_addr.eq(0b10), # NIA
 262              dmi_req.eq(1),
 263              dmi_wen.eq(0),
 264             )
 265         )
 266
 267         # kick off a "step"
 268         self.sync += If(dmicount == 8,
 269             (dmi_addr.eq(0), # CTRL
 270              dmi_din.eq(1<<3), # STEP
 271              dmi_req.eq(1),
 272              dmi_wen.eq(1),
 273              dmirunning.eq(0), # stop counter, need to fire "monitor"
 274              dmi_monitor.eq(1), # start "monitor" instead
 275             )
 276         )
 277
 278         # limit range of pc for debug reporting
 279         #self.comb += active_dbg.eq((0x378c <= pc) & (pc <= 0x38d8))
 280         #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58))
 281         self.comb += active_dbg.eq(1)
 282
 283
 284         # get the MSR
 285         self.sync += If(active_dbg & (dmicount == 12),
 286             (dmi_addr.eq(0b11), # MSR
 287              dmi_req.eq(1),
 288              dmi_wen.eq(0),
 289             )
 290         )
 291
 292         if cpu == "libresoc":
 293             self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x1094c))
 294             #self.comb += active_dbg_cr.eq(1)
 295
 296             # get the CR
 297             self.sync += If(active_dbg_cr & (dmicount == 16),
 298                 (dmi_addr.eq(0b1000), # CR
 299                  dmi_req.eq(1),
 300                  dmi_wen.eq(0),
 301                 )
 302             )
 303
 304         # read all 32 GPRs
 305         for i in range(32):
 306             self.sync += If(active_dbg & (dmicount == 20+(i*8)),
 307                 (dmi_addr.eq(0b100), # GSPR addr
 308                  dmi_din.eq(i), # r1
 309                  dmi_req.eq(1),
 310                  dmi_wen.eq(1),
 311                 )
 312             )
 313
 314             self.sync += If(active_dbg & (dmicount == 24+(i*8)),
 315                 (dmi_addr.eq(0b101), # GSPR data
 316                  dmi_req.eq(1),
 317                  dmi_wen.eq(0),
 318                 )
 319             )
 320
 321         # monitor bbus read/write
 322         self.sync += If(active_dbg & self.cpu.dbus.stb & self.cpu.dbus.ack,
 323             Display("    [%06x] dadr: %8x, we %d s %01x w %016x r: %016x",
 324                 #uptime,
 325                 0,
 326                 self.cpu.dbus.adr,
 327                 self.cpu.dbus.we,
 328                 self.cpu.dbus.sel,
 329                 self.cpu.dbus.dat_w,
 330                 self.cpu.dbus.dat_r
 331             )
 332         )
 333
 334         return
 335
 336         # monitor ibus write
 337         self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
 338                         self.cpu.ibus.we,
 339             Display("    [%06x] iadr: %8x, s %01x w %016x",
 340                 #uptime,
 341                 0,
 342                 self.cpu.ibus.adr,
 343                 self.cpu.ibus.sel,
 344                 self.cpu.ibus.dat_w,
 345             )
 346         )
 347         # monitor ibus read
 348         self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
 349                         ~self.cpu.ibus.we,
 350             Display("    [%06x] iadr: %8x, s %01x r %016x",
 351                 #uptime,
 352                 0,
 353                 self.cpu.ibus.adr,
 354                 self.cpu.ibus.sel,
 355                 self.cpu.ibus.dat_r
 356             )
 357         )
 358
 359 # Build -----------------------------------------------------------------------
 360
 361 def main():
 362     parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
 363     parser.add_argument("--cpu",          default="libresoc",
 364                         help="CPU to use: libresoc (default) or microwatt")
 365     parser.add_argument("--debug",        action="store_true",
 366                         help="Enable debug traces")
 367     parser.add_argument("--trace",        action="store_true",
 368                         help="Enable tracing")
 369     parser.add_argument("--trace-start",  default=0,
 370                         help="Cycle to start FST tracing")
 371     parser.add_argument("--trace-end",    default=-1,
 372                         help="Cycle to end FST tracing")
 373     args = parser.parse_args()
 374
 375     sim_config = SimConfig(default_clk="sys_clk")
 376     sim_config.add_module("serial2console", "serial")
 377
 378     for i in range(2):
 379         soc = LibreSoCSim(cpu=args.cpu, debug=args.debug)
 380         builder = Builder(soc,compile_gateware = i!=0)
 381         builder.build(sim_config=sim_config,
 382             run         = i!=0,
 383             trace       = args.trace,
 384             trace_start = int(args.trace_start),
 385             trace_end   = int(args.trace_end),
 386             trace_fst   = 0)
 387         os.chdir("../")
 388
 389 if __name__ == "__main__":
 390     main()