src/soc/litex/sim.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # This file is Copyright (c) 2020 Dolu1990 <charles.papon.90@gmail.com>
   5 # License: BSD
   6
   7 import os
   8 import argparse
   9
  10 from migen import ClockDomain
  11
  12 from litex.build.generic_platform import Pins, Subsignal
  13 from litex.build.sim import SimPlatform
  14 from litex.build.sim.config import SimConfig
  15
  16 from litex.soc.integration.soc import SoCRegion
  17 from litex.soc.integration.soc_core import SoCCore
  18 from litex.soc.integration.common import get_mem_data
  19 from litex.soc.integration.builder import Builder
  20
  21 from litedram.modules import MT41K128M16
  22 from litedram.phy.model import SDRAMPHYModel
  23 from litedram.core.controller import ControllerSettings
  24
  25 from litex.tools.litex_sim import get_sdram_phy_settings
  26
  27 from soc.litex.core import LibreSOC
  28
  29 # IOs ------------------------------------------------------------------
  30
  31 _io = [
  32     ("sys_clk", 0, Pins(1)),
  33     ("sys_rst", 0, Pins(1)),
  34     ("serial", 0,
  35         Subsignal("source_valid", Pins(1)),
  36         Subsignal("source_ready", Pins(1)),
  37         Subsignal("source_data",  Pins(8)),
  38
  39         Subsignal("sink_valid", Pins(1)),
  40         Subsignal("sink_ready", Pins(1)),
  41         Subsignal("sink_data",  Pins(8)),
  42     ),
  43 ]
  44
  45 # Platform --------------------------------------------------------------
  46
  47 class Platform(SimPlatform):
  48     def __init__(self):
  49         SimPlatform.__init__(self, "SIM", _io)
  50
  51 # SoCSMP ----------------------------------------------------------------
  52
  53 class SoCSMP(SoCCore):
  54     def __init__(self, cpu_variant, init_memories=False, with_sdcard=False):
  55         platform     = Platform()
  56         sys_clk_freq = int(100e6)
  57
  58         sdram_init = []
  59         if init_memories:
  60             sdram_init = get_mem_data({
  61                 "images/fw_jump.bin": "0x00f00000",
  62                 "images/Image":       "0x00000000",
  63                 "images/dtb"  :       "0x00ef0000",
  64                 "images/rootfs.cpio": "0x01000000",
  65                 }, "little")
  66
  67         # SoCCore --------------------------------------------------------
  68         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
  69             cpu_type                 = "microwatt", # XXX use microwatt
  70             cpu_variant              = cpu_variant,
  71             cpu_cls                  = LibreSOC,
  72             uart_name                = "sim",
  73             integrated_rom_size      = 0x8000,
  74             integrated_main_ram_size = 0x00000000)
  75
  76         self.platform.name = "sim"
  77         self.add_constant("SIM")
  78
  79         self.clock_domains.cd_sys = ClockDomain()
  80         self.comb += [
  81             self.cd_sys.clk.eq(platform.request("sys_clk")),
  82             self.cd_sys.rst.eq(platform.request("sys_rst"))
  83         ]
  84
  85         # SDRAM ----------------------------------------------------------
  86         phy_settings = get_sdram_phy_settings(
  87             memtype    = "DDR3",
  88             data_width = 16,
  89             clk_freq   = 100e6)
  90         self.submodules.sdrphy = SDRAMPHYModel(
  91             module    = MT41K128M16(100e6, "1:4"),
  92             settings  = phy_settings,
  93             clk_freq  = 100e6,
  94             init      = sdram_init)
  95         self.add_sdram("sdram",
  96             phy                     = self.sdrphy,
  97             module                  = MT41K128M16(100e6, "1:4"),
  98             origin                  = self.mem_map["main_ram"],
  99             controller_settings     = ControllerSettings(
 100                 cmd_buffer_buffered = False,
 101                 with_auto_precharge = True
 102             )
 103         )
 104         if init_memories:
 105             addr = 0x40f00000
 106             self.add_constant("MEMTEST_BUS_SIZE",  0) # Skip test if memory is
 107             self.add_constant("MEMTEST_ADDR_SIZE", 0) # initialized to avoid
 108             self.add_constant("MEMTEST_DATA_SIZE", 0) # corrumpting the content.
 109             self.add_constant("ROM_BOOT_ADDRESS", addr) # Jump to fw_jump.bin
 110         else:
 111             self.add_constant("MEMTEST_BUS_SIZE",  4096)
 112             self.add_constant("MEMTEST_ADDR_SIZE", 4096)
 113             self.add_constant("MEMTEST_DATA_SIZE", 4096)
 114
 115         # SDCard -----------------------------------------------------
 116         if with_sdcard:
 117             self.add_sdcard("sdcard", use_emulator=True)
 118
 119 # Build -----------------------------------------------------------------
 120
 121 def main():
 122     parser = argparse.ArgumentParser(
 123                         description="Linux on LiteX-LibreSOC Simulation")
 124     parser.add_argument("--cpu-variant", default="standard",
 125                         help="Select CPU netlist variant")
 126     parser.add_argument("--sdram-init",  action="store_true",
 127                         help="Init SDRAM with Linux images")
 128     parser.add_argument("--with-sdcard", action="store_true",
 129                         help="Enable SDCard support")
 130     parser.add_argument("--trace",       action="store_true",
 131                         help="Enable VCD tracing")
 132     parser.add_argument("--trace-start", default=0,
 133                         help="Cycle to start VCD tracing")
 134     parser.add_argument("--trace-end",   default=-1,
 135                         help="Cycle to end VCD tracing")
 136     parser.add_argument("--opt-level",   default="O3",
 137                         help="Compilation optimization level")
 138     args = parser.parse_args()
 139
 140     sim_config = SimConfig(default_clk="sys_clk")
 141     sim_config.add_module("serial2console", "serial")
 142
 143     for i in range(2):
 144         to_run = (i != 0) # first build (i=0), then run (i=1)
 145         soc = SoCSMP(args.cpu_variant, args.sdram_init and to_run,
 146                      args.with_sdcard)
 147         builder = Builder(soc,
 148             compile_gateware = to_run,
 149             csr_json         = "build/sim/csr.json")
 150         builder.build(sim_config=sim_config,
 151             run         = to_run,
 152             opt_level   = args.opt_level,
 153             trace       = args.trace,
 154             trace_start = int(args.trace_start),
 155             trace_end   = int(args.trace_end),
 156             trace_fst   = 1)
 157         os.chdir("../")
 158         #if not to_run:
 159         #  os.system("./json2dts.py build/sim/csr.json > build/sim/dts") # FIXME
 160         #  os.system("dtc -O dtb -o images/dtb build/sim/dts") # FIXME
 161         #  os.system("cp verilog/*.bin build/sim/gateware/")
 162
 163 if __name__ == "__main__":
 164     main()