src/soc/litex/sim.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # This file is Copyright (c) 2020 Dolu1990 <charles.papon.90@gmail.com>
   5 # License: BSD
   6
   7 import argparse
   8
   9 from migen import *
  10
  11 from litex.build.generic_platform import *
  12 from litex.build.sim import SimPlatform
  13 from litex.build.sim.config import SimConfig
  14
  15 from litex.soc.integration.soc import SoCRegion
  16 from litex.soc.integration.soc_core import *
  17 from litex.soc.integration.builder import *
  18
  19 from litedram.modules import MT41K128M16
  20 from litedram.phy.model import SDRAMPHYModel
  21 from litedram.core.controller import ControllerSettings
  22
  23 from litex.tools.litex_sim import get_sdram_phy_settings
  24
  25 from vexriscv_smp import VexRiscvSMP
  26
  27 # IOs ----------------------------------------------------------------------------------------------
  28
  29 _io = [
  30     ("sys_clk", 0, Pins(1)),
  31     ("sys_rst", 0, Pins(1)),
  32     ("serial", 0,
  33         Subsignal("source_valid", Pins(1)),
  34         Subsignal("source_ready", Pins(1)),
  35         Subsignal("source_data",  Pins(8)),
  36
  37         Subsignal("sink_valid", Pins(1)),
  38         Subsignal("sink_ready", Pins(1)),
  39         Subsignal("sink_data",  Pins(8)),
  40     ),
  41 ]
  42
  43 # Platform -----------------------------------------------------------------------------------------
  44
  45 class Platform(SimPlatform):
  46     def __init__(self):
  47         SimPlatform.__init__(self, "SIM", _io)
  48
  49 # SoCSMP -------------------------------------------------------------------------------------------
  50
  51 class SoCSMP(SoCCore):
  52     def __init__(self, cpu_variant, init_memories=False, with_sdcard=False):
  53         platform     = Platform()
  54         sys_clk_freq = int(100e6)
  55
  56         sdram_init = []
  57         if init_memories:
  58             sdram_init = get_mem_data({
  59                 "images/fw_jump.bin": "0x00f00000",
  60                 "images/Image":       "0x00000000",
  61                 "images/dtb"  :       "0x00ef0000",
  62                 "images/rootfs.cpio": "0x01000000",
  63                 }, "little")
  64
  65         # SoCCore ----------------------------------------------------------------------------------
  66         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
  67             cpu_type                 = "vexriscv", cpu_variant=cpu_variant, cpu_cls=VexRiscvSMP,
  68             uart_name                = "sim",
  69             integrated_rom_size      = 0x8000,
  70             integrated_main_ram_size = 0x00000000)
  71         self.platform.name = "sim"
  72         self.add_constant("SIM")
  73
  74         # PLIC ------------------------------------------------------------------------------------
  75         self.bus.add_slave("plic", self.cpu.plicbus, region=SoCRegion(origin=0xf0C00000, size=0x400000, cached=False))
  76         interrupt_map = {**SoCCore.interrupt_map, **{
  77             "uart":       1,
  78         }}
  79
  80         # CLINT ------------------------------------------------------------------------------------
  81         self.bus.add_slave("clint", self.cpu.cbus, region=SoCRegion(origin=0xf0010000, size=0x10000, cached=False))
  82
  83         # CRG --------------------------------------------------------------------------------------
  84         self.submodules.crg = CRG(platform.request("sys_clk"))
  85
  86         # SDRAM ------------------------------------------------------------------------------------
  87         phy_settings = get_sdram_phy_settings(
  88             memtype    = "DDR3",
  89             data_width = 16,
  90             clk_freq   = 100e6)
  91         self.submodules.sdrphy = SDRAMPHYModel(
  92             module    = MT41K128M16(100e6, "1:4"),
  93             settings  = phy_settings,
  94             clk_freq  = 100e6,
  95             init      = sdram_init)
  96         self.add_sdram("sdram",
  97             phy                     = self.sdrphy,
  98             module                  = MT41K128M16(100e6, "1:4"),
  99             origin                  = self.mem_map["main_ram"],
 100             controller_settings     = ControllerSettings(
 101                 cmd_buffer_buffered = False,
 102                 with_auto_precharge = True
 103             )
 104         )
 105         if init_memories:
 106             self.add_constant("MEMTEST_BUS_SIZE",  0) # Skip test if memory is initialized to avoid
 107             self.add_constant("MEMTEST_ADDR_SIZE", 0) # corrumpting the content.
 108             self.add_constant("MEMTEST_DATA_SIZE", 0)
 109             self.add_constant("ROM_BOOT_ADDRESS", 0x40f00000) # Jump to fw_jump.bin
 110         else:
 111             self.add_constant("MEMTEST_BUS_SIZE",  4096)
 112             self.add_constant("MEMTEST_ADDR_SIZE", 4096)
 113             self.add_constant("MEMTEST_DATA_SIZE", 4096)
 114
 115         # SDCard -----------------------------------------------------------------------------------
 116         if with_sdcard:
 117             self.add_sdcard("sdcard", use_emulator=True)
 118
 119 # Build --------------------------------------------------------------------------------------------
 120
 121 def main():
 122     parser = argparse.ArgumentParser(description="Linux on LiteX-VexRiscv Simulation")
 123     parser.add_argument("--cpu-variant",          default="2c",            help="Select CPU netlist variant")
 124     parser.add_argument("--sdram-init",           action="store_true",     help="Init SDRAM with Linux images")
 125     parser.add_argument("--with-sdcard",          action="store_true",     help="Enable SDCard support")
 126     parser.add_argument("--trace",                action="store_true",     help="Enable VCD tracing")
 127     parser.add_argument("--trace-start",          default=0,               help="Cycle to start VCD tracing")
 128     parser.add_argument("--trace-end",            default=-1,              help="Cycle to end VCD tracing")
 129     parser.add_argument("--opt-level",            default="O3",            help="Compilation optimization level")
 130     args = parser.parse_args()
 131
 132     sim_config = SimConfig(default_clk="sys_clk")
 133     sim_config.add_module("serial2console", "serial")
 134
 135     for i in range(2):
 136         soc = SoCSMP(args.cpu_variant, args.sdram_init and i!=0, args.with_sdcard)
 137         builder = Builder(soc,
 138             compile_gateware = i!=0,
 139             csr_json         = "build/sim/csr.json")
 140         builder.build(sim_config=sim_config,
 141             run         = i!=0,
 142             opt_level   = args.opt_level,
 143             trace       = args.trace,
 144             trace_start = int(args.trace_start),
 145             trace_end   = int(args.trace_end),
 146             trace_fst   = 1)
 147         os.chdir("../")
 148         if i == 0:
 149             os.system("./json2dts.py build/sim/csr.json > build/sim/dts") # FIXME
 150             os.system("dtc -O dtb -o images/dtb build/sim/dts")           # FIXME
 151             os.system("cp verilog/*.bin build/sim/gateware/")
 152
 153 if __name__ == "__main__":
 154     main()