src/soc/logical/bperm.py

   1 from nmigen import Elaboratable, Signal, Module, Repl, Cat, Const, Array
   2 from nmigen.cli import main
   3
   4 class Bpermd(Elaboratable):
   5     """This class does a Bit Permute on a Doubleword
   6
   7        X-form bpermd RA,RS,RB]
   8
   9        Eight permuted bits are produced. For each permuted bit i where i ranges
  10        from 0 to 7 and for each byte i of RS, do the following. If byte i of RS
  11        is less than 64, permuted bit i is setto the bit of RB specified by byte
  12        i of RS; otherwise permuted bit i is set to 0. The  permuted  bits are
  13        placed in the least-significantbyte of RA, and the remaining bits are
  14        filled with 0s.
  15        Special Registers Altered: None
  16
  17        Programming note:
  18        The fact that the permuted bit is 0 if the corresponding index value
  19        exceeds 63 permits the permuted bits to be selected from a 128-bit
  20        quantity, using a single index register. For example, assume that the
  21        128-bit quantity Q, from which the permuted bits are to be selected, is
  22        in registers r2(high-order 64 bits of Q) and r3 (low-order 64 bits of Q),
  23        that the index values are in register r1, with each byte of r1 containing
  24        a value in the range 0:127, and that each byte of register r4 contains
  25        the value 64. The following code sequence selects eight permuted bits
  26        from Q and places them into the low-order byte of r6.
  27     """
  28
  29     def __init__(self, width):
  30         self.perm = Signal(width)
  31         self.rs   = Signal(width)
  32         self.ra   = Signal(width)
  33         self.rb   = Signal(width)
  34
  35     def elaborate(self, platform):
  36         m = Module()
  37         index = Signal(8)
  38         signals = [ Signal(1) for i in range(64) ]
  39         for i,n in enumerate(signals):
  40             n.eq(self.rb[i])
  41         rb64 = Array(signals)
  42         for i in range(0, 8):
  43             index = self.rs[8 * i:8 * i + 8]
  44             with m.If(index < 64):
  45                 m.d.comb += self.perm[i].eq(rb64[index])
  46             with m.Else():
  47                 continue
  48         m.d.comb += self.ra[0:8].eq(self.perm)
  49         return m
  50
  51 if __name__ == "__main__":
  52     bperm = Bpermd(width=64)
  53     main(bperm,ports=[bperm.perm, bperm.rs, bperm.ra, bperm.rb])