src/soc/minerva/cache.py

   1 from nmigen import (Elaboratable, Module, Const, Signal, Record, Array,
   2                     Mux, Memory)
   3 from nmigen.asserts import Assume, Initial
   4 from nmigen.lib.coding import Encoder
   5 from nmigen.utils import log2_int
   6
   7
   8 __all__ = ["L1Cache"]
   9
  10
  11 class L1Cache(Elaboratable):
  12     def __init__(self, nways, nlines, nwords, base, limit):
  13         if not nlines or nlines & nlines-1:
  14             raise ValueError("nlines must be a power of 2, not {!r}".format(nlines))
  15         if nwords not in {4, 8, 16}:
  16             raise ValueError("nwords must be 4, 8 or 16, not {!r}".format(nwords))
  17         if nways not in {1, 2}:
  18             raise ValueError("nways must be 1 or 2, not {!r}".format(nways))
  19
  20         self.nways = nways
  21         self.nlines = nlines
  22         self.nwords = nwords
  23         self.base = base
  24         self.limit = limit
  25
  26         offsetbits = log2_int(nwords)
  27         linebits = log2_int(nlines)
  28         tagbits = log2_int(limit-base) - log2_int(nlines) - log2_int(nwords) - 2
  29
  30         self.s1_addr = Record([("offset", offsetbits), ("line", linebits), ("tag", tagbits)])
  31         self.s1_flush = Signal()
  32         self.s1_stall = Signal()
  33         self.s1_valid = Signal()
  34         self.s2_addr = Record.like(self.s1_addr)
  35         self.s2_re = Signal()
  36         self.s2_evict = Signal()
  37         self.s2_valid = Signal()
  38         self.bus_valid = Signal()
  39         self.bus_error = Signal()
  40         self.bus_rdata = Signal(32)
  41
  42         self.s2_miss = Signal()
  43         self.s2_rdata = Signal(32)
  44         self.bus_re = Signal()
  45         self.bus_addr = Record.like(self.s1_addr)
  46         self.bus_last = Signal()
  47
  48     def elaborate(self, platform):
  49         m = Module()
  50
  51         ways = Array(Record([("data",   self.nwords * 32),
  52                              ("tag",    self.s2_addr.tag.shape()),
  53                              ("valid",  1),
  54                              ("bus_re", 1)])
  55                      for _ in range(self.nways))
  56
  57         if self.nways == 1:
  58             way_lru = Const(0)
  59         elif self.nways == 2:
  60             way_lru = Signal()
  61             with m.If(self.bus_re & self.bus_valid & self.bus_last & ~self.bus_error):
  62                 m.d.sync += way_lru.eq(~way_lru)
  63
  64         m.d.comb += ways[way_lru].bus_re.eq(self.bus_re)
  65
  66         way_hit = m.submodules.way_hit = Encoder(self.nways)
  67         for j, way in enumerate(ways):
  68             m.d.comb += way_hit.i[j].eq((way.tag == self.s2_addr.tag) & way.valid)
  69
  70         m.d.comb += [
  71             self.s2_miss.eq(way_hit.n),
  72             self.s2_rdata.eq(ways[way_hit.o].data.word_select(self.s2_addr.offset, 32))
  73         ]
  74
  75         with m.FSM() as fsm:
  76             last_offset = Signal.like(self.s2_addr.offset)
  77
  78             with m.State("CHECK"):
  79                 with m.If(self.s2_re & self.s2_miss & self.s2_valid):
  80                     m.d.sync += [
  81                         self.bus_addr.eq(self.s2_addr),
  82                         self.bus_re.eq(1),
  83                         last_offset.eq(self.s2_addr.offset - 1)
  84                     ]
  85                     m.next = "REFILL"
  86
  87             with m.State("REFILL"):
  88                 m.d.comb += self.bus_last.eq(self.bus_addr.offset == last_offset)
  89                 with m.If(self.bus_valid):
  90                     m.d.sync += self.bus_addr.offset.eq(self.bus_addr.offset + 1)
  91                 with m.If(self.bus_valid & self.bus_last | self.bus_error):
  92                     m.d.sync += self.bus_re.eq(0)
  93                 with m.If(~self.bus_re & ~self.s1_stall):
  94                     m.next = "CHECK"
  95
  96         if platform == "formal":
  97             with m.If(Initial()):
  98                 m.d.comb += Assume(fsm.ongoing("CHECK"))
  99
 100         for way in ways:
 101             valid_lines = Signal(self.nlines)
 102
 103             with m.If(self.s1_flush & self.s1_valid):
 104                 m.d.sync += valid_lines.eq(0)
 105             with m.Elif(way.bus_re & self.bus_error):
 106                 m.d.sync += valid_lines.bit_select(self.bus_addr.line, 1).eq(0)
 107             with m.Elif(way.bus_re & self.bus_valid & self.bus_last):
 108                 m.d.sync += valid_lines.bit_select(self.bus_addr.line, 1).eq(1)
 109             with m.Elif(self.s2_evict & self.s2_valid & (way.tag == self.s2_addr.tag)):
 110                 m.d.sync += valid_lines.bit_select(self.s2_addr.line, 1).eq(0)
 111
 112             tag_mem = Memory(width=len(way.tag), depth=self.nlines)
 113             tag_rp = tag_mem.read_port()
 114             tag_wp = tag_mem.write_port()
 115             m.submodules += tag_rp, tag_wp
 116
 117             data_mem = Memory(width=len(way.data), depth=self.nlines)
 118             data_rp = data_mem.read_port()
 119             data_wp = data_mem.write_port(granularity=32)
 120             m.submodules += data_rp, data_wp
 121
 122             m.d.comb += [
 123                 tag_rp.addr.eq(Mux(self.s1_stall, self.s2_addr.line, self.s1_addr.line)),
 124                 data_rp.addr.eq(Mux(self.s1_stall, self.s2_addr.line, self.s1_addr.line)),
 125
 126                 tag_wp.addr.eq(self.bus_addr.line),
 127                 tag_wp.en.eq(way.bus_re & self.bus_valid & self.bus_last),
 128                 tag_wp.data.eq(self.bus_addr.tag),
 129
 130                 data_wp.addr.eq(self.bus_addr.line),
 131                 data_wp.en.bit_select(self.bus_addr.offset, 1).eq(way.bus_re & self.bus_valid),
 132                 data_wp.data.eq(self.bus_rdata << self.bus_addr.offset*32),
 133
 134                 way.valid.eq(valid_lines.bit_select(self.s2_addr.line, 1)),
 135                 way.tag.eq(tag_rp.data),
 136                 way.data.eq(data_rp.data)
 137             ]
 138
 139             if platform == "formal":
 140                 with m.If(Initial()):
 141                     m.d.comb += Assume(~valid_lines.bool())
 142
 143         return m