src/soc/minerva/cache.py

   1 from nmigen import (Elaboratable, Module, Const, Signal, Record, Array,
   2                     Mux, Memory)
   3 from nmigen.asserts import Assume, Initial
   4 from nmigen.lib.coding import Encoder
   5 from nmigen.utils import log2_int
   6
   7
   8 __all__ = ["L1Cache"]
   9
  10
  11 class L1Cache(Elaboratable):
  12     def __init__(self, nways, nlines, nwords, base, limit):
  13         if not nlines or nlines & nlines-1:
  14             raise ValueError("nlines must be a power "\
  15                              "of 2, not {!r}".format(nlines))
  16         if nwords not in {4, 8, 16}:
  17             raise ValueError("nwords must be 4, 8 or 16, "\
  18                              "not {!r}".format(nwords))
  19         if nways not in {1, 2}:
  20             raise ValueError("nways must be 1 or 2, not {!r}".format(nways))
  21
  22         self.nways = nways
  23         self.nlines = nlines
  24         self.nwords = nwords
  25         self.base = base
  26         self.limit = limit
  27
  28         offsetbits = log2_int(nwords)
  29         linebits = log2_int(nlines)
  30         tagbits = log2_int(limit-base) - log2_int(nlines) - log2_int(nwords) - 2
  31
  32         self.s1_addr = Record([("offset", offsetbits),
  33                                ("line", linebits),
  34                                ("tag", tagbits)])
  35         self.s1_flush = Signal()
  36         self.s1_stall = Signal()
  37         self.s1_valid = Signal()
  38         self.s2_addr = Record.like(self.s1_addr)
  39         self.s2_re = Signal()
  40         self.s2_evict = Signal()
  41         self.s2_valid = Signal()
  42         self.bus_valid = Signal()
  43         self.bus_error = Signal()
  44         self.bus_rdata = Signal(32)
  45
  46         self.s2_miss = Signal()
  47         self.s2_rdata = Signal(32)
  48         self.bus_re = Signal()
  49         self.bus_addr = Record.like(self.s1_addr)
  50         self.bus_last = Signal()
  51
  52     def elaborate(self, platform):
  53         m = Module()
  54
  55         ways = Array(Record([("data",   self.nwords * 32),
  56                              ("tag",    self.s2_addr.tag.shape()),
  57                              ("valid",  1),
  58                              ("bus_re", 1)])
  59                      for _ in range(self.nways))
  60
  61         if self.nways == 1:
  62             way_lru = Const(0)
  63         elif self.nways == 2:
  64             way_lru = Signal()
  65             with m.If(self.bus_re & self.bus_valid & self.bus_last &
  66                       ~self.bus_error):
  67                 m.d.sync += way_lru.eq(~way_lru)
  68
  69         m.d.comb += ways[way_lru].bus_re.eq(self.bus_re)
  70
  71         way_hit = m.submodules.way_hit = Encoder(self.nways)
  72         for j, way in enumerate(ways):
  73             hit = (way.tag == self.s2_addr.tag) & way.valid
  74             m.d.comb += way_hit.i[j].eq(hit)
  75
  76         m.d.comb += [
  77             rdata = ways[way_hit.o].data.word_select(self.s2_addr.offset, 32)
  78             self.s2_miss.eq(way_hit.n),
  79             self.s2_rdata.eq(rdata)
  80         ]
  81
  82         with m.FSM() as fsm:
  83             last_offs = Signal.like(self.s2_addr.offset)
  84
  85             with m.State("CHECK"):
  86                 with m.If(self.s2_re & self.s2_miss & self.s2_valid):
  87                     m.d.sync += [
  88                         self.bus_addr.eq(self.s2_addr),
  89                         self.bus_re.eq(1),
  90                         last_offs.eq(self.s2_addr.offset - 1)
  91                     ]
  92                     m.next = "REFILL"
  93
  94             with m.State("REFILL"):
  95                 m.d.comb += self.bus_last.eq(self.bus_addr.offset == last_offs)
  96                 with m.If(self.bus_valid):
  97                     m.d.sync += self.bus_addr.offset.eq(self.bus_addr.offset+1)
  98                 with m.If(self.bus_valid & self.bus_last | self.bus_error):
  99                     m.d.sync += self.bus_re.eq(0)
 100                 with m.If(~self.bus_re & ~self.s1_stall):
 101                     m.next = "CHECK"
 102
 103         if platform == "formal":
 104             with m.If(Initial()):
 105                 m.d.comb += Assume(fsm.ongoing("CHECK"))
 106
 107         for way in ways:
 108             valid_lines = Signal(self.nlines)
 109
 110             with m.If(self.s1_flush & self.s1_valid):
 111                 m.d.sync += valid_lines.eq(0)
 112             with m.Elif(way.bus_re & self.bus_error):
 113                 m.d.sync += valid_lines.bit_select(self.bus_addr.line, 1).eq(0)
 114             with m.Elif(way.bus_re & self.bus_valid & self.bus_last):
 115                 m.d.sync += valid_lines.bit_select(self.bus_addr.line, 1).eq(1)
 116             with m.Elif(self.s2_evict & self.s2_valid &
 117                         (way.tag == self.s2_addr.tag)):
 118                 m.d.sync += valid_lines.bit_select(self.s2_addr.line, 1).eq(0)
 119
 120             tag_mem = Memory(width=len(way.tag), depth=self.nlines)
 121             tag_rp = tag_mem.read_port()
 122             tag_wp = tag_mem.write_port()
 123             m.submodules += tag_rp, tag_wp
 124
 125             data_mem = Memory(width=len(way.data), depth=self.nlines)
 126             data_rp = data_mem.read_port()
 127             data_wp = data_mem.write_port(granularity=32)
 128             m.submodules += data_rp, data_wp
 129
 130             taddr = Mux(self.s1_stall, self.s2_addr.line, self.s1_addr.line)
 131             daddr = Mux(self.s1_stall, self.s2_addr.line, self.s1_addr.line)
 132             den = way.bus_re & self.bus_valid
 133             m.d.comb += [
 134                 tag_rp.addr.eq(taddr),
 135                 data_rp.addr.eq(daddr),
 136
 137                 tag_wp.addr.eq(self.bus_addr.line),
 138                 tag_wp.en.eq(way.bus_re & self.bus_valid & self.bus_last),
 139                 tag_wp.data.eq(self.bus_addr.tag),
 140
 141                 data_wp.addr.eq(self.bus_addr.line),
 142                 data_wp.en.bit_select(self.bus_addr.offset, 1).eq(den),
 143                 data_wp.data.eq(self.bus_rdata << self.bus_addr.offset*32),
 144
 145                 way.valid.eq(valid_lines.bit_select(self.s2_addr.line, 1)),
 146                 way.tag.eq(tag_rp.data),
 147                 way.data.eq(data_rp.data)
 148             ]
 149
 150             if platform == "formal":
 151                 with m.If(Initial()):
 152                     m.d.comb += Assume(~valid_lines.bool())
 153
 154         return m